Method and system for determining instruction conflict states for issuance of memory instructions in a VLIW processor

• US 10,241,788 B2
• Filed: 10/31/2014
• Issued: 03/26/2019
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Inventors: Kurd, Tariq, Redford, John
• Primary Examiner(s): Mehta, Jyoti
• Application Number:
  US14/530,104
• Publication Number:
  US 20150309798A1
• Time in Patent Office: 1,607 Days
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/325 for loops, e.g. loop detection or loop counter
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3848 using hybrid branch prediction, e.g. selection between prediction techniques
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

An apparatus including a queue configured to store a plurality of instructions and state information indicating whether each instruction of the plurality of instructions can be performed independently of older pending instructions; and a state-selection circuit configured to set a state information of each instruction of the plurality of instructions in view of an older pending instruction in the queue.

Claims

1. A method, comprising:

receiving, by a first queue, and storing therein, an instruction of a first plurality of instructions that updates a first physical resource of a plurality of physical resources, the instruction being not ready to execute;

transferring the instruction from the first queue to a second queue in response to the instruction becoming ready to execute;

comparing, by a state-selection circuit, the instruction against an older instruction of a second plurality of instructions, the second plurality of instructions being stored in the second queue and the older instruction requiring a second physical resource of the plurality of physical resources;

setting a status in the second queue, by the state-selection circuit, to indicate whether (i) the instruction can be issued independent of the older instruction;

or (ii) the instruction must be issued, if at all, after the older instruction is issued;

issuing one of the instruction and the older instruction from the second queue;

identifying resource-independent instructions from instructions stored in the second queue; and

in response to the identifying, issuing resource-independent instructions that update more of the plurality of physical resources before resource-independent instructions that update fewer of the plurality of physical resources.

2. The method of claim 1, wherein the instruction and the older instruction are concurrently pending in the second queue.

3. The method of claim 1, wherein the comparing comprises:

comparing the instruction against the older instruction within a single processor clock cycle.

4. The method of claim 1, wherein the setting is responsive to the instruction being transferred to the second queue.

5. The method of claim 4, wherein the comparing is responsive to the instruction being transferred to the second queue.

6. The method of claim 1, wherein the instruction and the older instruction are issued independently when the first physical resource is not the same as the second physical resource.

7. An apparatus, comprising:

a first queue configured to store a first plurality of instructions, each instruction of the first plurality of instructions being not ready to execute;

a second queue, coupled to the first queue, configured to store a second plurality of instructions and a plurality of state information, the plurality of state information indicating whether each instruction of the second plurality of instructions can be performed independently of any older pending instruction of the second plurality of instructions, wherein the second queue is further configured to receive instructions from the first queue responsive to those instructions of the first queue becoming ready to execute;

a state-selection circuit configured to set a state information of each instruction of the second plurality of instructions in view of an older pending instruction in the second queue; and

state update and issue determination circuitry configured to identify resource-independent instructions from instructions stored in the second queue, and, in response to identifying the resource-independent instructions, to issue resource-independent instructions that update more of a plurality of physical resources before resource-independent instructions that update fewer of the plurality of physical resources.

8. The apparatus of claim 7, wherein each of the second plurality of instructions update a physical resource of the plurality of physical resources.

9. The apparatus of claim 7, wherein the state-selection circuit is further configured to generate the state information of each of the second plurality of instructions of the second queue in a single processor cycle.

10. The apparatus of claim 7, wherein the state-selection circuit is further configured to generate a new state information to be included with the plurality of state information responsive to a new instruction being transferred to the second queue.

11. The apparatus of claim 7, wherein the state-selection circuit is further configured to set a state information from among the plurality of state information to indicate an instruction, of the second plurality of instructions, corresponding to the state information is independent if the instruction does not access a same physical resource of the plurality of physical resources as any older instruction of the second plurality of instructions.

12. The apparatus of claim 7, wherein the state-selection circuit is further configured to set a state information from among the plurality of state information to indicate that an instruction, of the second plurality of instructions, corresponding to the state information cannot be issued if the instruction does access a same physical resource of the plurality of physical resources as at least one older instruction of the second plurality of instructions.

13. A method, comprising:

comparing, by a state-selection circuit, an instruction against an older instruction of a plurality of instructions stored in a queue;

setting a status in the queue, by the state-selection circuit, to indicate whether (i) the instruction can be issued independent of the older instruction;

or (ii) the instruction must be issued, if at all, after the older instruction is issued;

issuing one of the instruction and the older instruction from the queue;

identifying resource-independent instructions from instructions stored in the queue; and

in response to the identifying, issuing resource-independent instructions that update more of a plurality of physical resources before resource-independent instructions that update fewer of the plurality of physical resources.

14. The method of claim 13, wherein the instruction and the older instruction are concurrently pending in the queue.

15. The method of claim 13, wherein the comparing comprises:

comparing the instruction against the older instruction in the queue within a single processor clock cycle.

16. The method of claim 15, wherein the comparing occurs responsive to the instruction being transferred to the queue from another queue.

17. The method of claim 13, wherein the setting is responsive to the instruction being transferred to the queue from another queue.

18. The method of claim 13, wherein the instruction updates a first physical resource of the plurality of physical resources and the older instruction updates a second physical resource of the plurality of physical resources.

19. The method of claim 18, wherein the instruction and the older instruction are issued independently when the first physical resource is not the same as the second physical resource.