Memory system and method of controlling nonvolatile memory

• US 10,241,859 B2
• Filed: 09/01/2017
• Issued: 03/26/2019
• Est. Priority Date: 07/23/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Kanno, Shinichi
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US15/694,471
• Publication Number:
  US 20180011760A1
• Time in Patent Office: 571 Days
• Field of Search: 714763
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/611 Specific encoding aspects, e.g. encoding by means of decoding

Abstract

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages a plurality of namespaces for storing a plurality of kinds of data having different update frequencies. The controller encodes write data by using first coding for reducing wear of a memory cell to generate first encoded data, and generates second encoded data to be written to the nonvolatile memory by adding an error correction code to the first encoded data. The controller changes the ratio between the first encoded data and the error correction code based on the namespace to which the write data is to be written.

Claims

1. A memory system comprising:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and configured to;

manage a plurality of areas of the nonvolatile memory, the areas including a first area for storing a first type of data and a second area for storing a second type of data having a lower update frequency than the first type of data,

encode write data by using first coding for reducing wear of a memory cell to generate first encoded data,

generate second encoded data by adding an error correction code to the first encoded data, the second encoded data including the first encoded data and the error correction code, and

write the second encoded data to one of the first area and the second area,

wherein the first encoded data corresponding to the first type has a first length and the error correction code corresponding to the first type has a second length, and wherein the first encoded data corresponding to the second type has a third length less than the first length and the error correction code corresponding to the second type has a fourth length greater than the second length.

2. The memory system of claim 1, wherein the encoding the write data includes converting a first code in the write data into another code longer than the first code.

3. The memory system of claim 1, wherein the controller is configured to compress the write data, and encode the compressed write data by using the first coding to generate the first encoded data.

4. The memory system of claim 3, wherein the first encoded data is longer than the compressed write data.

5. The memory system of claim 1, wherein the controller is configured to change a ratio between the first encoded data and the error correction code based on an update frequency of the write data.

6. A memory system comprising:

a nonvolatile memory; and

a controller electrically connected to the nonvolatile memory and configured to;

logically divide the nonvolatile memory into a plurality of areas, the areas including a first area for storing a first type of data and a second area for storing a second type of data having a lower update frequency than the first type of data,

encode write data by using first coding for reducing wear of a memory cell to generate first encoded data,

generate second encoded data by adding an error correction code to the first encoded data, the second encoded data including the first encoded data and the error correction code, and

write the second encoded data to one of the first area and the second area,

wherein the first encoded data corresponding to the first type has a first length and the error correction code corresponding to the first type has a second length, and wherein the first encoded data corresponding to the second type has a third length less than the first length and the error correction code corresponding to the second type has a fourth length greater than the second length.

7. The memory system of claim 6, wherein the controller is configured to change a ratio between the first encoded data and the error correction code based on an update frequency of the write data.

8. A method of controlling a nonvolatile memory, the method comprising:

managing a plurality of areas of the nonvolatile memory, the areas including a first area for storing a first type of data and a second area for storing a second type of data having a lower update frequency than the first type of data;

encoding write data by using first coding for reducing wear of a memory cell to generate first encoded data;

generating second encoded data by adding an error correction code to the first encoded data, the second encoded data including the first encoded data and the error correction code; and

writing the second encoded data to one of the first area and the second area,

wherein the first encoded data corresponding to the first type has a first length and the error correction code corresponding to the first type has a second length, and wherein the first encoded data corresponding to the second type has a third length less than the first length and the error correction code corresponding to the second type has a fourth length greater than the second length.

9. The method of claim 8, wherein the encoding the write data includes converting a first code in the write data into another code longer than the first code.

10. The method of claim 8, further comprising:

compressing the write data, wherein

the first encoded data is generated by encoding the compressed write data by using the first coding.

11. The method of claim 10, wherein the first encoded data is longer than the compressed write data.

12. The method of claim 8, further comprising:

changing a ratio between the first encoded data and the error correction code based on an update frequency of the write data.