Predictive 3-D virtual fabrication system and method

• US 10,242,142 B2
• Filed: 03/14/2013
• Issued: 03/26/2019
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Coventor, Inc. (Lam Research Corporation)
• Original Assignee: Coventor, Inc. (Lam Research Corporation)
• Inventors: Greiner, Kenneth B., Breit, Stephen R., Fried, David M., Faken, Daniel
• Primary Examiner(s): Lee, Eric
• Application Number:
  US13/831,440
• Publication Number:
  US 20140282324A1
• Time in Patent Office: 2,203 Days
• Field of Search: 716 51
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A virtual fabrication environment for semiconductor device structures that includes the use of virtual metrology measurement data to optimize a virtual fabrication sequence is described. Further, calibration of the virtual fabrication environment is performed by comparing virtual metrology data generated from a virtual fabrication run with a subset of measurements performed in a physical fabrication environment. Additionally, virtual experiments conducted in the virtual fabrication environment of the present invention generate multiple device structure models using ranges of process and design parameter variations for an integrated process flow and design space of interest.

Claims

1. A non-transitory computer-readable medium holding computer-executable instructions for virtually fabricating a semiconductor device structure, the instructions when executed causing the computing device to:

receive a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated;

add a user-supplied measurement locator shape to a layer in 2D design data for the structure;

insert a user-supplied virtual metrology measurement step into the process sequence prior to the end of the process sequence, the virtual metrology measurement step indicating a point during the process sequence at which a measurement should be taken using the locator shape;

perform with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and material removal steps needed to physically fabricate the semiconductor device structure, the virtual fabrication run;

executing the process sequence up until the virtual metrology measurement step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure,

performing the measurement indicated by the virtual metrology measurement step on the 3D structural model within a region indicated by the locator shape, and

executing additional steps in the process sequence after the measurement, the virtual fabrication run completing the building of the 3D structural model, the 3D structural model displayed to a user in a 3D view; and

export virtual metrology measurement data generated from the virtual metrology measurement step of the virtual fabrication run.

2. The medium of claim 1 wherein the instructions when executed further cause the computing device to:

receive a user-supplied modification to the process sequence or 2D design data following the user viewing the exported virtual metrology measurement data.

3. The medium of claim 2 wherein the instructions when executed further cause the computing device to:

perform an additional virtual fabrication run for the semiconductor device structure using the modification; and

export virtual metrology measurement data generated during the additional virtual fabrication run.

4. The medium of claim 1 wherein the instructions when executed further cause the computing device to:

compare the virtual metrology measurement data from the virtual fabrication run with a measurement taken during a corresponding physical fabrication run; and

receive a user direction to adjust a process parameter in the process sequence based on the comparing to calibrate the process sequence.

5. The medium of claim 1 wherein the instructions when executed further cause the computing device to:

receive a specification of a set of parameter variations for the process sequence or the 2D design data; and

perform a plurality of virtual fabrication runs in a virtual experiment that build a plurality of 3D structural models using the parameter variations,

wherein the virtual metrology measurement data is generated for each parameter variation.

6. The medium of claim 5 wherein the virtual metrology measurement data that is generated for each parameter variation is parsed and presented to a user.

7. The medium of claim 5 wherein the set of parameter variations are for the process sequence and the process sequence is previously calibrated by comparing the virtual metrology measurement data from the virtual fabrication run with a measurement taken for a corresponding physical fabrication run and adjusting a process parameter based on the comparing.

8. A computing device-implemented method of virtually fabricating a semiconductor device structure, comprising:

receiving a selection of a process sequence in a process editor for a semiconductor device structure to be virtually fabricated;

adding a user-supplied measurement locator shape to a layer in 2D design data for the semiconductor device structure;

inserting a user-supplied virtual metrology measurement step into the process sequence prior to the end of the process sequence, the virtual metrology measurement step indicating a point during the process sequence at which a measurement should be taken using the locator shape;

performing with the computing device a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and material removal steps needed to physically fabricate the semiconductor device structure, the virtual fabrication run;

executing the process sequence up until the virtual metrology measurement step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure,

performing the measurement indicated by the virtual metrology measurement step on the 3D structural model within a region indicated by the locator shape, and

executing additional steps in the process sequence after the measurement, the virtual fabrication run completing the building of the 3D structural model, the 3D structural model displayed to a user in a 3D view; and

exporting virtual metrology measurement data generated from the virtual metrology measurement step of the virtual fabrication run.

9. The method of claim 8, further comprising:

receiving a user-supplied modification to the process sequence or 2D design data following the user viewing the exported virtual metrology measurement data.

10. The method of claim 8, further comprising:

performing an additional virtual fabrication run for the semiconductor device structure using the modification; and

exporting virtual metrology measurement data generated during the additional virtual fabrication run.

11. The method of claim 8, further comprising:

compare the virtual metrology measurement data from the virtual fabrication run with a measurement taken during a corresponding physical fabrication run; and

adjusting a process parameter in the process sequence to calibrate the process sequence based on the comparing.

12. The method of claim 8, further comprising:

receiving a specification of a set of parameter variations for the process sequence or the 2D design data; and

performing a plurality of virtual fabrication runs in a virtual experiment that build a plurality of 3D structural models using the parameter variations,

wherein the virtual metrology measurement data is generated for each parameter variation.

13. The method of claim 12 wherein the virtual metrology measurement data that is generated for each parameter variation is parsed and presented to a user.

14. The method of claim 12 wherein the set of parameter variations are for the process sequence and the process sequence is previously calibrated by comparing the virtual metrology measurement data from the virtual fabrication run with a measurement taken for a corresponding physical fabrication run and adjusting a process parameter based on the comparing.

15. A virtual fabrication system, comprising:

a computing device equipped with a processor and configured to receive input data with a 3D modeling engine, the input data including 2D design data and a process sequence for a semiconductor device structure to be virtually fabricated, the process sequence including a user-supplied virtual metrology measurement step indicating a point during the process sequence prior to the end of the process sequence at which a measurement should be taken using a locator shape added to the 2D design data, the computing device configured to perform a virtual fabrication run that models an integrated process flow used to physically fabricate the semiconductor device structure by using the process sequence and 2D design data to simulate patterning, material addition and material removal steps needed to physically fabricate the semiconductor device structure, the performing;

executing the process sequence up until the virtual metrology measurement step, the executing building a 3D structural model of the semiconductor device structure, the 3D structural model predictive of a result of a physical fabrication of the semiconductor device structure,

performing the measurement indicated by the virtual metrology measurement step on the 3D structural model within a region indicated by the locator shape,

executing additional steps in the process sequence after the measurement, the virtual fabrication run completing the building of the 3D structural model, the 3D structural model displayed to a user in a 3D view, and

exporting the virtual metrology measurement data; and

a display surface in communication with the computing device, the display surface configured to display the 3D structural model in a 3D view.

16. The virtual fabrication system of claim 15 wherein the process sequence in the virtual fabrication run is calibrated by comparing the virtual metrology measurement data from the virtual fabrication run with a measurement taken during a corresponding physical fabrication run and adjusting a process parameter in the process sequence based on the comparing.

17. The virtual fabrication system of claim 15 wherein a plurality of virtual fabrication runs that build a plurality of 3D structural models in a virtual experiment are performed using a set of parameter variations for the process sequence or the 2D design data, the virtual metrology measurement data being generated for each parameter variation.

18. The virtual fabrication system of claim 17, further comprising:

a plurality of cores or processors for performing the plurality of virtual fabrication runs in parallel.

19. The virtual fabrication system of claim 17, further comprising:

a hierarchical materials database.