Circuit design implementation using control-set based merging and module-based replication

• US 10,242,150 B1
• Filed: 06/07/2016
• Issued: 03/26/2019
• Est. Priority Date: 06/07/2016
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Das, Sabyasachi, Yang, Xiaojian, Shah, Niyati, Keshavdas, Govinda, Revenu, Frederic
• Primary Examiner(s): Parihar, Suchin
• Application Number:
  US15/175,897
• Time in Patent Office: 1,022 Days
• Field of Search: 716114
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Circuit design implementation can include selecting a first and second load each having a control pin of a same type driven by a different driver, determining whether the driver of the first load matches the driver of the second load, and modifying the circuit design to drive the control pins of the first load and the second load using the driver of the first load. Circuit design implementation can include selecting a net having a driver and a plurality of loads exceeding a threshold, determining a selected module of the circuit design having a number of the plurality of loads of the net that meet a cloning criteria, and, in response, modifying the circuit design by creating a clone of the driver within the selected module and driving each load of the net within the selected module with the clone of the driver.

Claims

1. A method of circuit design implementation using controls sets, comprising:

selecting, using a processor, a first load and a second load each having a control pin of a same type driven by a different driver, wherein the control pins receive control signals that are distinct from data signals received by the first load and the second load;

determining, using the processor, that the driver of the first load matches the driver of the second load; and

responsive to the determining, modifying the circuit design, using the processor, to drive the control pins of the first load and the second load using the driver of the first load;

wherein the modified circuit design is implemented within an integrated circuit device.

2. The method of claim 1, wherein the determining that the driver of the first load matches the driver of the second load comprises:

determining that the driver of the first load and the driver of the second load are of a same type of circuit component; and

determining that input connectivity of the driver of the first load matches the input connectivity of the driver of the second load.

3. The method of claim 1, wherein the modifying the circuit design comprises:

removing the driver of the first load from the circuit design.

4. The method of claim 1, wherein the modifying the circuit design comprises:

disconnecting the control pin of the first load from the driver of the first load;

removing the driver of the first load from the circuit design; and

connecting the control pin of the first load to the driver of the second load.

5. The method of claim 1, wherein the determining that the driver of the first load matches the driver of the second load comprises:

determining that neither the driver of the first load nor the driver of the second load is associated with a constraint.

6. The method of claim 1, further comprising:

responsive to determining that an upstream pair of drivers for the first load and the second load match, performing a driver merge operation on the upstream pair of drivers.

7. The method of claim 1, further comprising:

performing the determining whether the driver of the first load matches the driver of the second load and the modifying the circuit design for different control pins of the first load and the second load of a different control pin type.

8. The method of claim 1, wherein the determining that the driver of the first load matches the driver of the second load comprises:

determining that the driver of the first load and the driver of the second load are assigned to a same group based upon timing information.

9. The method of claim 1, further comprising:

first forming a group of loads having same types of control pins where the control pins are driven by different drivers, wherein the first load and the second load are selected from the group.

10. The method of claim 9, wherein the selecting, the determining, and the modifying are performed for each pair of loads of the group.

11. A method of circuit design implementation using module-based replication, comprising:

selecting, using a processor, a net having a driver and a plurality of loads exceeding a high fan-out net threshold;

determining, using the processor, a selected module of the circuit design having a number of the plurality of loads of the net that meets at least one cloning criterion;

grouping the loads of the selected module into a plurality of groups based on timing; and

responsive to the determining and grouping, modifying, using the processor, the circuit design by creating one clone of the driver for each group of the plurality of groups in the selected module of the circuit design, wherein each clone drives the loads in the group corresponding to the clone;

wherein the modified circuit design is implemented within an integrated circuit device.

12. The method of claim 11, wherein the modifying the circuit design comprises:

disconnecting each of the loads of the net within the selected module from the driver; and

connecting each of the loads of the net within the selected module to the corresponding clones of the driver.

13. The method of claim 11, wherein the at least one cloning criterion includes a lower threshold number of loads of the selected module.

14. The method of claim 13, wherein the selected module is a lowest level module of the circuit design.

15. The method of claim 13, wherein the at least one cloning criterion includes an upper threshold number of loads of the selected module that is less than the high fan-out net threshold.

16. The method of claim 11, further comprising:

identifying a plurality of modules of the circuit design that collectively have a number of loads of the net that meets the at least one cloning criterion and using the identified plurality of modules as the selected module, wherein the clone of the driver drives the loads of the plurality of modules.

17. The method of claim 11, further comprising:

comparing an original count of loads of the net with a sum of loads driven by the driver of the net and loads driven by each clone of the driver to perform verification.

18. The method of claim 11, wherein a first group of the plurality of groups and a second group of the plurality of groups are timing constrained to different degrees.

19. The method of claim 11, wherein the grouping is performed based on slack.