Device structure for neuromorphic computing system
First Claim
1. A device comprising:
- an array of resistance cells having a number M of rows and a number N of columns of resistance cells, resistance cells in the array each comprising a transistor having a threshold representing a weight factor Wnm of the cell, and a resistive element in series with the transistor, the cell having a cell resistance having a first value when the transistor is on and a second value when the transistor is off;
a set of source lines coupled to the resistance cells in respective columns of resistance cells;
a set of bit lines coupled to the resistance cells in respective rows of resistance cells, signals on the bit lines in the set of bit lines representing inputs x(m) to the respective rows;
a set of word lines coupled to gates of the transistors in the resistance cells in respective columns of resistance cells, signals on the word lines in the set of word lines selecting respective columns of resistance cells; and
a set of sensing circuits coupled to respective source lines in the set of source lines,wherein current sensed at a particular source line in the set of source lines represents a sum of products of the inputs x(m) by respective weight factors Wnm.
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Abstract
An array of resistance cells has a number M of rows and a number N of columns of resistance cells. Each cell comprises a transistor having a threshold, representing a weight factor Wnm of the cell, and a resistive element in series with the transistor. Each cell has a cell resistance having a first value when the transistor is on and a second value when the transistor is off. A set of source lines is coupled to the resistance cells in respective columns. A set of bit lines is coupled to the resistance cells in respective rows, signals on the bit lines representing inputs x(m) to the respective rows. A set of word lines is coupled to gates of the transistors in the resistance cells in respective columns. Current sensed at a particular source line represents a sum of products of the inputs x(m) by respective weight factors Wnm.
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Citations
20 Claims
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1. A device comprising:
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an array of resistance cells having a number M of rows and a number N of columns of resistance cells, resistance cells in the array each comprising a transistor having a threshold representing a weight factor Wnm of the cell, and a resistive element in series with the transistor, the cell having a cell resistance having a first value when the transistor is on and a second value when the transistor is off; a set of source lines coupled to the resistance cells in respective columns of resistance cells; a set of bit lines coupled to the resistance cells in respective rows of resistance cells, signals on the bit lines in the set of bit lines representing inputs x(m) to the respective rows; a set of word lines coupled to gates of the transistors in the resistance cells in respective columns of resistance cells, signals on the word lines in the set of word lines selecting respective columns of resistance cells; and a set of sensing circuits coupled to respective source lines in the set of source lines, wherein current sensed at a particular source line in the set of source lines represents a sum of products of the inputs x(m) by respective weight factors Wnm. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of manufacturing a memory device, comprising:
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forming an array of resistance cells having a number M of rows and a number N of columns of resistance cells, resistance cells in the array each comprising a transistor having a threshold, representing a weight factor Wnm of the cell, and a resistive element in series with the transistor, the cell having a cell resistance having a first value when the transistor is on and a second value when the transistor is off; forming a set of source lines coupled to the resistance cells in respective columns of resistance cells; forming a set of bit lines coupled to the resistance cells in respective rows of resistance cells, signals on the bit lines in the set of bit lines representing inputs x(m) to the respective rows; forming a set of word lines coupled to gates of the transistors in the resistance cells in respective columns of resistance cells, signals on the word lines in the set of word lines selecting respective columns of resistance cells; and forming a set of sensing circuits coupled to respective source lines in the set of source lines, wherein current sensed at a particular source line in the set of source lines represents a sum of products of the inputs x(m) by respective weight factors Wnm. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification