Calibration apparatus and method for sampler with adjustable high frequency gain

• US 10,242,749 B2
• Filed: 04/21/2017
• Issued: 03/26/2019
• Est. Priority Date: 04/22/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin, Hormati, Ali
• Primary Examiner(s): Cox, Cassandra
• Application Number:
  US15/494,435
• Publication Number:
  US 20170309346A1
• Time in Patent Office: 704 Days
• Field of Search: None
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H03K 2005/00013 Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
• CPC Class Codes: H03K 5/01 Shaping pulses discrimination against noise or interference H03K5/125
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling interval by enabling a current source according to a first transition of the received sampling signal, generating a differential output voltage at the pair of output nodes by discharging the pair of output nodes according to a differential input signal, the pair of output nodes discharged according to current drawn by the current source during the sampling interval, terminating the sampling interval by disabling the current source in response to a second transition of the received sampling signal, and inhibiting a recharge of the pair of output nodes for a hold time after termination of the sampling interval and prior to initiation of a subsequent sampling interval.

Claims

1. A method comprising:

receiving a sampling signal;

pre-charging a pair of output nodes prior to a sampling interval;

initiating the sampling interval by enabling a current source according to a first transition of the received sampling signal;

generating a differential output voltage at the pair of output nodes by discharging the pair of output nodes according to a differential input signal, the pair of output nodes discharged according to current drawn by the current source during the sampling interval;

terminating the sampling interval by disabling the current source in response to a second transition of the received sampling signal; and

inhibiting a recharge of the pair of output nodes for a hold time after termination of the sampling interval and prior to initiation of a subsequent sampling interval.

2. The method of claim 1, wherein the first transition is a rising-edge transition and wherein the second transition is a falling-edge transition.

3. The method of claim 1, wherein the first transition is a falling-edge transition and wherein the second transition is a rising-edge transition.

4. The method of claim 1, further comprising:

coupling the pair of output nodes to a reset-inhibition transistor after termination of the sampling interval via a pair of transistors, each transistor in the pair of transistors receiving the sampling signal;

receiving, at the reset-inhibition transistor, a phase-offset signal having a phase offset with respect to the sampling signal; and

inhibiting the recharge of the pair of output nodes by preventing current flow from a charging supply to the pair of output nodes via the pair of transistors during the hold time, the hold time corresponding to the phase offset.

5. The method of claim 4, wherein the received sampling signal and phase-offset signal are clock signals.

6. The method of claim 5, further wherein the clock signals are generated by a clock signal generator.

7. The method of claim 1, wherein inhibiting the recharge of the pair of output nodes comprises receiving a reset-enable at a pair of reset-inhibition transistors, and pre-charging the pair of output nodes according to the reset-enable signal.

8. The method of claim 7, wherein the reset-enable signal is generated using a reset-enable signal generator.

9. The method of claim 8, wherein the reset-enable signal generator comprises an XOR gate for generating the reset-enable signal by XOR'"'"'ing the sampling signal and a delayed version of the sampling signal.

10. The method of claim 1, further comprising latching the differential output voltage.

11. An apparatus comprising:

a sampler configured to form a differential output voltage at a pair of output nodes, the sampler comprising;

a current source configured to receive a sampling signal, the current source configured to initiate a sampling interval by enabling the current source according to a first transition of the received sampling signal and terminate the sampling interval by disabling the current source according to a second transition of the received sampling signal; and

a differential transistor pair connected to the current source and to the pair of output nodes, the differential transistor pair configured to receive a differential input signal and to responsively form the differential voltage output at the pair of output nodes based on current drawn by the current source during the sampling interval; and

a reset circuit connected to the pair of output nodes, the reset circuit configured to pre-charge the pair of output nodes prior to initiation of the sampling interval, and to inhibit a recharge of the pair of output nodes for a hold time after termination of the sampling interval and prior to initiation of a subsequent sampling interval.

12. The apparatus of claim 11, wherein the first transition is a rising-edge transition and wherein the second transition is a falling-edge transition.

13. The apparatus of claim 11, wherein the first transition is a falling-edge transition and wherein the second transition is a rising-edge transition.

14. The apparatus of claim 11, wherein the reset circuit comprises:

a pair of transistors connected to the pair of output nodes and to a reset-inhibition transistor, each transistor in the pair of transistors configured to receive the sampling signal and to couple the pair of output nodes to the reset-inhibition transistor after termination of the sampling interval; and

the reset-inhibition transistor further connected to a charging source, the inhibiting transistor configured to receive a phase-offset signal having a phase offset with respect to the sampling signal, the inhibiting transistor configured to inhibit the recharge of the pair of output nodes by preventing current flow from the charging supply to the pair of output nodes via the pair of transistors during the hold time, the hold time corresponding to the phase offset.

15. The apparatus of claim 14, wherein the received sampling signal and phase-offset signal are clock signals.

16. The apparatus of claim 15, further comprising a clock signal generator configured to generate the clock signal and the phase-offset clock signal.

17. The apparatus of claim 11, wherein the reset circuit comprises a pair of reset-inhibition transistors connected to the pair of output nodes and a charging supply, the reset-inhibition transistors configured to receive a reset-enable signal and to pre-charge the pair of output nodes according to the reset-enable signal.

18. The apparatus of claim 17, further comprising a reset-enable signal generator configured to generate the reset-enable signal.

19. The apparatus of claim 18, wherein the reset-enable signal generator comprises a logical XOR configured to receive the sampling signal and a delayed version of the sampling signal, and to responsively generate the reset-enable signal.

20. The apparatus of claim 11, further comprising a latch configured to latch the differential output voltage.