Airgap formation with damage-free copper

• US 10,242,908 B2
• Filed: 11/14/2016
• Issued: 03/26/2019
• Est. Priority Date: 11/14/2016
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Kang, Sean, Ko, Jungmin, Luere, Oliver
• Primary Examiner(s): Culbert, Roberts P
• Application Number:
  US15/350,713
• Publication Number:
  US 20180138075A1
• Time in Patent Office: 862 Days
• Field of Search: None
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76826 by contacting the layer with gases, liquids or plasmas
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

Abstract

Processing methods may be performed to remove unwanted materials from a substrate, such as an oxide footing. The methods may include forming an inert plasma within a processing region of a processing chamber. Effluents of the inert plasma may be utilized to modify a surface of an exposed material on a semiconductor substrate within the processing region of the semiconductor chamber. A remote plasma may be formed from a fluorine-containing precursor to produce plasma effluents. The methods may include flowing the plasma effluents to the processing region of the semiconductor processing chamber. The methods may also include removing the modified surface of the exposed material from the semiconductor substrate.

Claims

1. An etching method comprising:

forming an inert plasma within a processing region of a semiconductor processing chamber;

modifying a surface of an exposed material on a semiconductor substrate within the processing region of the semiconductor processing chamber with effluents of the inert plasma, wherein the exposed material on the semiconductor substrate comprises a silicon-containing material located proximate a copper wire positioned along the semiconductor substrate;

forming a remote plasma from a fluorine-containing precursor to produce plasma effluents;

flowing the plasma effluents to the processing region of the semiconductor processing chamber; and

removing the modified surface of the exposed material from the semiconductor substrate.

2. The etching method of claim 1, wherein the inert plasma comprises a helium plasma.

3. The etching method of claim 1, wherein the inert plasma is formed from a bias power below about 200 W.

4. The etching method of claim 1, wherein the surface of the exposed material on the semiconductor substrate is modified to a depth from the exposed surface within the semiconductor substrate of less than about 15 nm.

5. The etching method of claim 1, wherein a pressure within the semiconductor processing chamber while forming the inert plasma and during the modifying is maintained below about 50 mTorr.

6. The etching method of claim 1, wherein the remote plasma is formed in a region of the semiconductor processing chamber fluidly isolated from the processing region of the semiconductor processing chamber or is formed in a remote plasma unit fluidly coupled with the semiconductor processing chamber.

7. The etching method of claim 1, wherein the semiconductor substrate is maintained at a temperature above or about 80°

C. during the removal of the modified surface of the exposed material.

8. The etching method of claim 7, wherein removing the modified surface of the exposed material exposes an unmodified portion of the material, and wherein an etching selectivity of a modified portion of the material to the unmodified portion of the material is greater than or about 100:

1.

9. The etching method of claim 1, wherein the remote plasma is additionally formed from a hydrogen-containing precursor.

10. The etching method of claim 1, wherein each operation of the etching method is repeated in at least one additional cycle, and wherein a total removal after all cycles is greater than or about 50 nm.

11. An etching method comprising:

forming an inert plasma within a processing region of a semiconductor processing chamber;

modifying an exposed region of dielectric on a semiconductor substrate within the processing region of the semiconductor processing chamber with effluents of the inert plasma, wherein the modifying reduces an amount of carbon within the region of dielectric;

contacting the modified dielectric with plasma effluents of a fluorine-containing precursor; and

etching the modified dielectric, wherein the modifying, contacting, and etching are all performed in the semiconductor processing chamber.

12. The etching method of claim 11, wherein the etching is performed at a temperature of greater than or about 80°

C.

13. The etching method of claim 11, wherein the plasma effluents of the fluorine-containing precursor are formed in a remote region of the semiconductor processing chamber fluidly coupled with, and physically separated from, the processing region of the semiconductor processing chamber.

14. The etching method of claim 13, wherein the plasma effluents of the fluorine-containing precursor are produced by a capacitively-coupled plasma at a power level of about 300 W.

15. The etching method of claim 13, wherein the modified dielectric is additionally contacted with a hydrogen-containing precursor.

16. The etching method of claim 15, wherein the hydrogen-containing precursor bypasses the remote region of the semiconductor processing chamber, and wherein the hydrogen-containing precursor interacts with the plasma effluents of the fluorine-containing precursor subsequent to the plasma effluents of the fluorine-containing precursor exiting the remote region of the semiconductor processing chamber.

17. An etching method comprising:

forming an inert plasma within a processing region of a semiconductor processing chamber, wherein the inert plasma comprises a hydrogen plasma formed by a bias power of less than or about 200 W;

modifying an exposed region of carbon-containing material on a semiconductor substrate within the processing region of the semiconductor processing chamber with effluents of the inert plasma, wherein the exposed region of carbon-containing material comprises a dielectric material positioned between copper interconnects formed on the semiconductor substrate, wherein a pressure within the semiconductor processing chamber is maintained below about 50 mTorr during the modifying;

forming a plasma of a fluorine-containing precursor in a remote region of the semiconductor processing chamber that is separated from the processing region of the semiconductor processing chamber by a showerhead;

contacting the modified dielectric material with plasma effluents of the fluorine-containing precursor; and

etching the modified dielectric material at a temperature of at least about 80°

C., wherein the modifying, contacting, and etching are all performed in the semiconductor processing chamber, and wherein no solid byproducts are produced during the etching.

18. The etching method of claim 17, wherein the remote region of the semiconductor processing chamber is a region defined within the semiconductor processing chamber.

19. The etching method of claim 17, wherein the remote region of the semiconductor processing chamber is a region external to the semiconductor processing chamber, but fluidly coupled with an inlet to the semiconductor processing chamber.