Semiconductor device, method of manufacturing the same and generation method of unique information

• US 10,242,950 B2
• Filed: 06/23/2017
• Issued: 03/26/2019
• Est. Priority Date: 06/24/2016
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Yano, Masaru, Wang, Pin-Yao
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US15/631,889
• Publication Number:
  US 20170373015A1
• Time in Patent Office: 641 Days
• Field of Search: 716110, 716 54, 716 56, 700 98, 700111, 700121, 326 41, 326 47, 326101, 257798, 438 5, 438 48, 438800
• CPC Class Codes: G05B 19/128 the workpiece itself serves as a record carrier, e.g. by its form, by marks or codes on it
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G09C 1/00 Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system cryptographic typewriters G09C3/00
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors

Abstract

A semiconductor device with improved generation function of unique information is provided. The semiconductor device includes an integrated circuit designed or fabricated based on a general design condition or manufacturing condition, an input/output circuit, and a unique-information generation circuit to generate unique information of the semiconductor device. The unique-information generation circuit includes a circuit for PUF and a code-generation unit. The circuit for PUF is fabricated based on the design condition or manufacturing condition which is different from the general design condition or manufacturing condition and has a factor which makes variations of circuit components become large. The code-generation unit generates codes based on the output of the circuit for PUF.

Claims

1. A method of manufacturing a semiconductor device having a function of generating unique information based on an output of a circuit component of a second circuit, the method comprising:

manufacturing a first circuit and the second circuit;

manufacturing the first circuit in accordance with a first manufacturing condition; and

manufacturing the second circuit in accordance with a second manufacturing condition;

when the second manufacturing condition is compared with the first manufacturing condition, the second manufacturing condition further includes a factor which increases a variation of the circuit component;

wherein the first manufacturing condition comprises setting a diffusion region of a first transistor having a channel length less than a constant value as an LDD structure and performing a channel-ion implantation by forming a first dopant concentration on a surface of a substrate;

wherein the second manufacturing condition comprises not setting a diffusion region of a second transistor having a channel length less than the constant value as the LDD structure and performing the channel-ion implantation by forming the first dopant concentration at a first position that is deeper than the surface of the substrate.

2. The method as claimed in claim 1, wherein:

the first circuit is designed in accordance with a first design condition;

the second circuit is designed in accordance with a second design condition; and

when the second design condition is compared with the first design condition, the second design condition further includes the factor which increases the variation of the circuit component.

3. The method as claimed in claim 2, wherein:

the first design condition comprises setting a channel width of the first transistor as a channel width W1;

the second design condition comprises setting a channel width of a second transistor as a channel width W2 which is less than the channel width W1.

4. The method as claimed in claim 3, wherein:

the channel width W1 is a design-allowable value;

the channel width W2 is a value that is less than the design-allowable value.

5. The method as claimed in claim 1, wherein:

the first manufacturing condition comprises performing the channel-ion implantation by forming a second dopant concentration, which is higher than the first dopant concentration, at a second position that is deeper than the surface of the substrate;

the second manufacturing condition comprises performing the channel-ion implantation by forming the second dopant concentration on the surface of the substrate.

6. A method of generating unique information of a semiconductor device, comprising:

manufacturing a first circuit in accordance with a first manufacturing condition;

manufacturing a second circuit in accordance with a second manufacturing condition, wherein when the second manufacturing condition is compared with the first manufacturing condition, the second manufacturing condition further includes a factor which increases a variation of a circuit component; and

generating the unique information based on an output of the circuit component of the second circuit;

wherein the first manufacturing condition comprises setting a diffusion region of a first transistor having a channel length less than a constant value as an LDD structure and performing a channel-ion implantation by forming a first dopant concentration on a surface of a substrate;

the second manufacturing condition comprises not setting a diffusion region of a second transistor having a channel length less than the constant value as the LDD structure and performing the channel-ion implantation by forming the first dopant concentration at a first position that is deeper than the surface of the substrate.

7. The method as claimed in claim 6, wherein the first circuit is designed in accordance with a first design condition and the second circuit is designed in accordance with a second design condition;

when the second design condition is compared with the first design condition, the second design condition further includes the factor which increases the variation of the circuit component.

8. The method as claimed in claim 7, wherein:

the first design condition comprises setting a channel width of a first transistor as a channel width W1;

the second design condition comprises setting a channel width of a second transistor as a channel width W2 which is less than the channel width W1.

9. A semiconductor device, comprising:

a first circuit manufactured in accordance with a first manufacturing condition;

a second circuit manufactured in accordance with a second manufacturing condition, wherein when the second manufacturing condition is compared with the first manufacturing condition, the second manufacturing condition further includes a factor which increases a variation of a circuit component; and

a generation circuit, generating unique information based on an output of a circuit component of the second circuit;

wherein the first manufacturing condition comprises setting a diffusion region of a first transistor having a channel length less than a constant value as an LDD structure and performing a channel-ion implantation by forming a first dopant concentration on a surface of a substrate;

the second manufacturing condition comprises not setting a diffusion region of a second transistor having a channel length less than the constant value as the LDD structure and performing the channel-ion implantation by forming the first dopant concentration at a first position that is deeper than the surface of the substrate.

10. The semiconductor device as claimed in claim 9, wherein:

the second circuit comprises a plurality of transistors connected in parallel;

the generation circuit comprises a detection circuit and a coding unit;

the detection circuit is provided to detect drain currents of the transistors which are turned on;

the coding unit generates coding information based on an output of the detection circuit.

11. The semiconductor device as claimed in claim 9, wherein:

the second circuit comprises multiple sets of inverters, and each set of inverters has two inverters;

the generation circuit includes a circuit which compares the voltage differences between different sets of inverters, when the sets of inverters have leakage currents, to generate a comparison result, and the circuit generates coding information based on the comparison result.

12. The semiconductor device as claimed in claim 9, wherein:

the first circuit is further manufactured in accordance with a first design condition; and

the second circuit is further manufactured in accordance with a second design condition, wherein when the second design condition is compared with the first design condition, the second design condition further includes the factor which increases the variation of the circuit component.