Semiconductor structure and manufacturing method thereof and terminal area structure of semiconductor device

• US 10,243,036 B2
• Filed: 01/12/2018
• Issued: 03/26/2019
• Est. Priority Date: 05/19/2017
• Status: Active Grant

• Current Assignee: uPI Semiconductor Corporation
• Original Assignee: UBIQ Semiconductor Corp.
• Inventors: Tsai, Yi-Yun, Chen, Chih-Hung, Chen, Chin-Fu
• Primary Examiner(s): Turner, Brian
• Application Number:
  US15/869,086
• Publication Number:
  US 20180337229A1
• Time in Patent Office: 438 Days
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor structure including a substrate, a first dielectric layer, a first conductive layer, a positioning part, two spacers, and a second conductive layer is provided. The substrate has a first trench. The first dielectric layer is disposed on a surface of the first trench. The first conductive layer is filled in the first trench and located on the first dielectric layer. The positioning part is disposed on the substrate and has a first opening. The first opening exposes the first trench. The spacers are disposed on two sidewalls of the first opening and expose the first conductive layer. The second conductive layer is filled in the first opening and electrically connected to the first conductive layer. The semiconductor structure can prevent the generation of leakage current while maintaining a high breakdown voltage.

Claims

1. A semiconductor structure, comprising:

a substrate having a first trench;

a first dielectric layer disposed on a surface of the first trench;

a first conductive layer filled in the first trench and located on the first dielectric layer;

a positioning part disposed on the substrate and having a first opening, wherein the first opening exposes the first trench;

two spacers disposed on two sidewalls of the first opening and exposing the first conductive layer;

a second dielectric layer disposed on the positioning part and having a second opening, wherein the second opening exposes the first opening; and

a second conductive layer filled in the first opening and electrically connected to the first conductive layer, wherein the second conductive layer is further extended and disposed in the second opening.

2. The semiconductor structure of claim 1, wherein a width of the first opening is greater than or equal to a width of the first trench.

3. The semiconductor structure of claim 1, wherein the two spacers at least cover a part of the first dielectric layer.

4. The semiconductor structure of claim 1, wherein a spacing between the two spacers decreases from top to bottom.

5. The semiconductor structure of claim 1, further comprising a third conductive layer disposed on the second dielectric layer and on the second conductive layer.

6. A manufacturing method of a semiconductor structure, comprising:

providing a substrate, wherein the substrate has a first trench;

forming a first dielectric layer on a surface of the first trench;

forming a first conductive layer on the first dielectric layer in the first trench;

forming a positioning part on the substrate, wherein the positioning part has a first opening, and the first opening exposes the first trench;

forming two spacers on two sidewalls of the first opening, wherein the first conductive layer is exposed between the two spacers;

forming a second dielectric layer on the positioning part;

performing a patterning process on the second dielectric layer to form a second opening in the second dielectric layer, wherein the second opening exposes the first opening; and

forming a second conductive layer filled in the first opening, wherein the second conductive layer is electrically connected to the first conductive layer, and the second conductive layer is further extended and disposed in the second opening.

7. The manufacturing method of the semiconductor structure of claim 6, wherein a forming method of the positioning part comprises:

forming a positioning material layer on the substrate; and

performing a patterning process on the positioning material layer.

8. The manufacturing method of the semiconductor structure of claim 6, wherein a width of the first opening is greater than or equal to a width of the first trench.

9. The manufacturing method of the semiconductor structure of claim 6, wherein a forming method of the two spacers comprises:

forming a spacer material layer on the first opening; and

performing an etch-back process on the spacer material layer.

10. The manufacturing method of the semiconductor structure of claim 6, wherein the two spacers at least cover a part of the first dielectric layer.

11. The manufacturing method of the semiconductor structure of claim 6, wherein a spacing between the two spacers decreases from top to bottom.

12. The manufacturing method of the semiconductor structure of claim 6, further comprising forming a third conductive layer on the second dielectric layer and on the second conductive layer.

13. A terminal area structure of a semiconductor device, comprising:

a substrate having a first trench and second trenches, wherein the first trench is intersected with the second trenches;

a first dielectric layer disposed on a surface of the first trench and on a surface of the second trenches;

a first conductive layer filled in the first trench and the second trenches and located on the first dielectric layer;

a positioning part disposed on the substrate and having a first opening, wherein the first opening exposes the first trench;

two spacers disposed on two sidewalls of the first opening and exposing the first conductive layer;

a second dielectric layer disposed on the positioning part and having a second opening, wherein the second opening exposes the first opening; and

a second conductive layer filled in the first opening and electrically connected to the first conductive layer, wherein the second conductive layer is further extended and disposed in the second opening.

14. The terminal area structure of the semiconductor device of claim 13, wherein the second trenches are parallel to one another.

15. The terminal area structure of the semiconductor device of claim 13, wherein the two spacers at least cover a part of the first dielectric layer.

16. The terminal area structure of the semiconductor device of claim 13, wherein the first trench and the second trenches are formed in a same process.