Transistor device with a field electrode that includes two layers

• US 10,243,051 B2
• Filed: 07/31/2017
• Issued: 03/26/2019
• Est. Priority Date: 08/01/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Feil, Thomas
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US15/663,903
• Publication Number:
  US 20180033859A1
• Time in Patent Office: 603 Days
• Field of Search: 438156, 438173, 438272, 257282, 257329, 257488
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/435 Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Disclosed is a transistor device and a method for producing a transistor device. The transistor device includes: a source region, a drift region, and a body region arranged between the source region and the drift region; a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric; and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. The field electrode includes at least two layers of different electrically conductive materials.

Claims

1. A method, comprising:

forming a source region, a body region and a drift region in a semiconductor body such that the body region is arranged between the source region and the drift region;

forming a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric; and

forming a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric such that the field electrode includes at least two layers of different electrically conductive materials,

wherein the at least two layers comprise a first layer adjoining the field electrode dielectric and a second layer adjoining the first layer,

wherein the first layer comprises a first material selected from the group consisting of;

a metal;

a metal nitride; and

a metal silicide,

wherein the semiconductor body comprises a first surface,

wherein a width direction of the field electrode is parallel to the first surface,

wherein the first layer comprises two vertical sections that extend in a vertical direction that is perpendicular to the first surface, and

wherein, in the width direction of the field electrode, the second layer is laterally contained between two vertical sections of the first layer.

2. The method of claim 1, wherein the metal is selected from the group consisting of:

titanium (Ti);

tungsten (W);

cobalt (Co); and

tantalum (Ta).

3. The method of claim 1, wherein the first layer has a lower electrical resistance than the second layer.

4. The method of claim 1, wherein the field electrode has a width smaller than 100 nanometers.

5. The method of claim 1, wherein forming the field electrode and the field electrode dielectric comprises:

forming a first trench in a first surface of the semiconductor body;

forming the field electrode dielectric on sidewalls and a bottom of the first trench;

forming the first layer on the field electrode dielectric; and

forming the second layer on the first layer.

6. The method of claim 5, further comprising:

forming the gate electrode and the gate electrode dielectric in the first trench between the field electrode and the first surface.

7. The method of claim 5,

wherein forming the field electrode dielectric comprises forming a dielectric layer on the sidewalls and the bottom of the first trench and on the first surface such that a first residual trench remains,

wherein forming the field electrode comprises forming the first layer such that the first layer covers the dielectric layer and such that a second residual trench remains and forming the second layer such that the second layer fills the second residual trench.

8. The method of claim 7, wherein forming the field electrode further comprises:

etching back the first layer and the second layer to form a third residual trench between the first layer and the second layer and the first surface.

9. The method of claim 8, wherein forming the field electrode dielectric comprises:

etching back the dielectric layer.

10. A transistor device, comprising:

a semiconductor body comprising a first surface;

a source region;

a drift region;

a body region being arranged between the source region and the drift region;

a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric; and

a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric,

wherein the field electrode includes at least two layers of different electrically conductive materials,

wherein the at least two layers comprise a first layer adjoining the field electrode dielectric and a second layer adjoining the first layer,

wherein the first layer comprises a first material selected from the group consisting of;

a metal;

a metal nitride; and

a metal silicide,

wherein a width direction of the field electrode is parallel to the first surface,

wherein the first layer comprises two vertical sections that extend in a vertical direction that is perpendicular to the first surface, and

wherein, in the width direction of the field electrode, the second layer is laterally contained between two vertical sections of the first layer.

11. The transistor device of claim 10, wherein the field electrode and the field electrode dielectric are formed in a first trench in the semiconductor body, wherein the first layer comprises a u-shaped structure formed along the field electrode dielectric in a bottom portion of the first trench, and wherein the second layer completely fills a central opening in the u-shaped structure.

12. The transistor device of claim 10, wherein the metal is selected from the group consisting of:

titanium (Ti);

tungsten (W);

cobalt (Co); and

tantalum (Ta).

13. The transistor device of claim 10, wherein the first layer has a lower electrical resistance than the second layer.

14. The transistor device of claim 10, wherein a width of the field electrode is smaller than 100 nanometers.

15. The transistor device of claim 10, wherein the second layer comprises polysilicon.

16. The transistor device of claim 10, wherein the second layer directly contacts the first layer.

17. The transistor device of claim 10, further comprising:

an additional trench adjoining the first trench at a longitudinal end of the first trench; and

a contact electrode in the additional trench and electrically connected to the field electrode.

18. The transistor device of claim 17, wherein the transistor device comprises a plurality of field electrodes, and wherein each of the plurality of field electrodes is connected to the contact electrode.

19. The transistor device of claim 10, wherein the field electrode and the field electrode dielectric are arranged in a first trench of a semiconductor body.

20. The transistor device of claim 19, wherein the gate electrode and the gate dielectric are arranged in a second trench spaced apart from the first trench.

21. The transistor device of claim 19, wherein the gate electrode and the gate dielectric are arranged in the first trench.

22. The transistor device of claim 21, wherein the gate electrode is dielectrically insulated from the field electrode in the first trench.

23. The transistor device of claim 21, wherein the gate electrode is electrically connected to the field electrode in the first trench.