Nanosheet transistor

• US 10,243,061 B1
• Filed: 11/15/2017
• Issued: 03/26/2019
• Est. Priority Date: 11/15/2017
• Status: Active Grant

• Current Assignee: Tessera (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Li, Juntao, Wu, Heng, Xu, Peng
• Primary Examiner(s): Picardat, Kevin M
• Application Number:
  US15/814,376
• Time in Patent Office: 496 Days
• Field of Search: None
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 23/291 Oxides or nitrides or carbides, e.g. ceramics, glass
• CPC Class Codes: H01L 23/3171 the coating being directly applied to the semiconductor body, e.g. passivation layer H01L23/3178 takes precedence
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/6681 using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.

Claims

1. A method of fabricating a nanosheet field-effect transistor, comprising:

obtaining a structure including a vertical stack of nanosheet channel layers and sacrificial silicon germanium layers, the nanosheet channel layers and sacrificial silicon germanium layers being arranged in alternating sequence;

forming a dielectric dummy gate on the vertical stack;

recessing portions of the vertical stack, thereby exposing first lateral edge portions of the channel layers and second lateral edge portions of the sacrificial silicon germanium layers;

oxidizing the first lateral edge portions and the second lateral edge portions, wherein first oxide layers and second oxide layers are formed from the first lateral edge portions and the second lateral edge portions, respectively, the second oxide layers having greater thickness than the first oxide layers;

removing the first oxide layers from the nanosheet channel layers;

epitaxially growing source/drain regions on the nanosheet channel layers;

narrowing the width of the dielectric dummy gate;

depositing a dielectric material over the dummy gate and the source/drain regions, thereby forming a dielectric liner over the dummy gate and the source/drain regions;

removing the dummy gate to form a trench within the dielectric liner;

removing the sacrificial silicon germanium layers to form spaces between the nanosheet channel layers;

forming a gate dielectric layer within the trench and on the nanosheet channel layers; and

depositing gate metal over the gate dielectric layer within the trench and within the spaces between the nanosheet channel layers.

2. The method of claim 1, wherein the nanosheet channel layers consist essentially of monocrystalline silicon.

3. The method of claim 1, further including:

depositing an interlevel dielectric layer on the dielectric liner.

4. The method of claim 3, wherein the dielectric liner consists essentially of SiCO.

5. The method of claim 3, wherein forming the gate dielectric layer further includes causing portions of the gate dielectric layer to adjoin the second oxide layers.

6. The method of claim 3, wherein:

the structure further includes a substrate and a dielectric surface layer on the substrate, the vertical stack extending vertically from the dielectric surface layer, and further wherein recessing portions of the vertical stack include removing the portions of the vertical stack down to the dielectric surface layer.

7. The method of claim 1, further including:

removing the second oxide layers from the sacrificial silicon germanium layers, thereby forming end spaces adjoining each sacrificial silicon germanium layer, wherein;

depositing the dielectric material to form the dielectric liner further includes causing the dielectric material to form inner dielectric spacers within the end spaces, and

forming the gate dielectric layer further includes causing portions of the gate dielectric layer to adjoin the dielectric liner within the end spaces.

8. The method of claim 7, wherein the dielectric liner consists essentially of SiCO.

9. The method of claim 1, wherein narrowing the width of the dielectric dummy gate causes the width of the dielectric dummy gate to be less than the distance between the first lateral edge portions of the channel layers.

10. The method of claim 9, further including forming dielectric inner spacers between the nanosheet channel layers from the second oxide layers or the dielectric material forming the dielectric liner.

11. A method of fabricating a nanosheet field-effect transistor, comprising:

obtaining a structure including;

a vertical stack of nanosheet channel layers and sacrificial silicon germanium layers, the nanosheet channel layers and sacrificial silicon germanium layers being arranged in alternating sequence,

epitaxial source/drain regions on the nanosheet channel layers,

a plurality of end spaces, each end space being between one of the sacrificial silicon germanium layers and one of the source/drain regions, and

a dielectric dummy gate having sidewalls extending vertically from a top surface of the vertical stack;

depositing a dielectric material over the dummy gate and the source/drain regions whereby the dielectric material further extends into the end spaces, thereby forming outer dielectric spacers over the sidewalls of the dummy gate, inner dielectric spacers between the sacrificial silicon germanium layers and the source/drain regions, and a dielectric liner over the source/drain regions;

forming an interlevel dielectric layer over the dielectric liner;

removing the dielectric dummy gate to form a trench within the outer dielectric spacers;

removing the sacrificial silicon germanium layers to form spaces between the nanosheet channel layers;

forming a gate dielectric layer within the trench and on the nanosheet channel layers; and

depositing gate metal over the gate dielectric layer within the trench and within the spaces between the nanosheet channel layers.

12. The method of claim 11, wherein the widths of the nanosheet channel layers exceed the width of the dielectric dummy gate.

13. The method of claim 12, wherein depositing the dielectric material includes conformally depositing SiCO.