Semiconductor device and method for manufacturing the same

• US 10,243,067 B2
• Filed: 12/11/2014
• Issued: 03/26/2019
• Est. Priority Date: 03/19/2014
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Konishi, Kazuya, Fukada, Yusuke, Narazaki, Atsushi
• Primary Examiner(s): Stark, Jarrett J
• Assistant Examiner(s): Ausar-El, Charles N
• Application Number:
  US14/567,354
• Publication Number:
  US 20150270378A1
• Time in Patent Office: 1,566 Days
• Field of Search: 257139
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a first semiconductor layer on one main surface of a semiconductor substrate; a plurality of trench gates in the first semiconductor layer extending to reach the inside of the semiconductor substrate; a second semiconductor layer selectively provided in an upper portion of the first semiconductor layer between the trench gates; an isolation layer in contact with a side surface of the second semiconductor layer and extends in the first semiconductor; and a third semiconductor layer in the upper portion of the first semiconductor layer between the trench gates and has at least one side surface in contact with the trench gate. The isolation layer is between and separates the second semiconductor layer and the third semiconductor layer from each other and is formed to extend to the same depth as, or to a position deeper than the second semiconductor layer.

Claims

1. A semiconductor device, comprising:

a first semiconductor layer of a second conductivity type disposed on one main surface of a semiconductor substrate of a first conductivity type;

a plurality of trench gates penetrating said first semiconductor layer in a thickness direction to reach the inside of said semiconductor substrate;

a second semiconductor layer of the second conductivity type selectively provided in an upper portion of said first semiconductor layer between said trench gates;

an isolation layer that is in contact with a side surface of said second semiconductor layer and extends in said first semiconductor layer in the thickness direction;

a third semiconductor layer of the first conductivity type that is provided in the upper portion of said first semiconductor layer between said trench gates and has at least one side surface in contact with said trench gate and at least one other side surface in contact with said isolation layer;

a first main electrode disposed on said first semiconductor layer so as to come into contact with said second semiconductor layer and said third semiconductor layer; and

a second main electrode provided on the other main surface side opposite to said one main surface of said semiconductor substrate,

wherein said isolation layer is provided between said second semiconductor layer and said third semiconductor layer to separate said second and third semiconductor layers from each other and is formed to extend to the same depth as that of said second semiconductor layer or to a position deeper than that of said second semiconductor layer,

said second semiconductor layer comprises a bottom surface that is in contact with said first semiconductor layer, and

a thickness of said isolation layer and said second semiconductor layer is at least twice that of said third semiconductor layer.

2. The semiconductor device according to claim 1, wherein said second semiconductor layer is formed deeper than said third semiconductor layer.

3. The semiconductor device according to claim 1, wherein said isolation layer includes:

a trench formed to extend in said first semiconductor layer in the thickness direction; and

an insulating layer filled in said trench, and said trench has a width larger than a dimension of an alignment accuracy upon formation of said second semiconductor layer and said third semiconductor layer.

4. The semiconductor device according to claim 1, wherein said isolation layer includes:

a trench formed to extend in said first semiconductor layer in the thickness direction; and

a conductor filled in said trench.

5. The semiconductor device according to claim 1, wherein said isolation layer includes:

a trench formed to extend in said first semiconductor layer in the thickness direction;

a silicon oxide film formed to cover an inner surface of said trench; and

a polysilicon layer that fills said trench and has conductivity.

6. The semiconductor device according to claim 1, wherein said second semiconductor layer has an impurity concentration of 5×

10¹⁹ to 5×

10²⁰/cm³.

7. The semiconductor device according to claim 1, wherein said third semiconductor layer has an impurity concentration of 5×

10¹⁹ to 5×

10²⁰/cm³.

8. The semiconductor device according to claim 1, wherein

said trench gates have a stripe shape in plan view and are disposed in a direction orthogonal to their extending direction,

said second semiconductor layer and said third semiconductor layer are provided alternately between said trench gates in the extending direction of said trench gates, and

said isolation layer is provided between said second semiconductor layer and said third semiconductor layer to extend between said trench gates.

9. The semiconductor device according to claim 1, wherein

said trench gates have a stripe shape in plan view and are disposed in a direction orthogonal to their extending direction,

a plurality of said second semiconductor layers are disposed with intervals in an extending direction of said trench gates between said trench gates,

said isolation layer is provided to surround each of said second semiconductor layers, and

said third semiconductor layer is provided in a portion between said trench gates except for said second semiconductor layers and said isolation layer.

10. The semiconductor device according to claim 1, wherein

a plurality of said second semiconductor layers are disposed with regular intervals in a surface of said first semiconductor layer,

said isolation layer is provided to surround each of said second semiconductor layers,

said third semiconductor layer is provided so as to surround said isolation layer,

said trench gates are provided to further surround an outer periphery of said third semiconductor layer, and

regions surrounded by said trench gates are disposed closely to each other.

11. A method for manufacturing the semiconductor device according to claim 1, wherein said isolation layer is formed before said second semiconductor layer is formed.

12. The method for manufacturing the semiconductor device according to claim 11, wherein

said isolation layer is formed by selectively ion-implanting oxygen into said first semiconductor layer.

13. The method for manufacturing the semiconductor device according to claim 11, wherein

each of said plurality of trench gates includes:

a first trench provided to penetrate said first semiconductor layer in a thickness direction to reach the inside of said semiconductor substrate;

a silicon oxide film formed to cover an inner surface of said first trench; and

a polysilicon layer that fills said first trench and has conductivity,

said isolation layer includes;

a second trench formed to extend in said first semiconductor layer in the thickness direction;

said silicon oxide film formed to cover an inner surface of said second trench; and

said polysilicon layer filled in said second trench, and

said trench gates and said isolation layer are simultaneously formed.

14. The semiconductor device according to claim 1, wherein

said first main electrode is an emitter electrode, and

said second main electrode is a collector electrode.