Transistor with field electrode

• US 10,243,071 B2
• Filed: 12/22/2016
• Issued: 03/26/2019
• Est. Priority Date: 12/30/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Zundel, Markus, Hirler, Franz
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US15/387,706
• Publication Number:
  US 20170194484A1
• Time in Patent Office: 824 Days
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 29/08 with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Disclosed is a transistor device and a method for producing thereof. The transistor device includes at least one transistor cell, wherein the at least one transistor cell includes: a source region, a body region and a drift region in a semiconductor body; a gate electrode dielectrically insulated from the body region by a gate dielectric; a field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a contact plug extending from a first surface of the semiconductor body to the field electrode and adjoining the source region and the body region.

Claims

1. A method comprising:

epitaxially growing a semiconductor layer on a surface of a semiconductor body, wherein the semiconductor body includes at least one field electrode dielectric and a field electrode in a trench of the semiconductor body, and wherein epitaxially growing the semiconductor layer comprises laterally overgrowing the field electrode dielectric with the semiconductor layer so as to completely laterally cover the at least one field electrode dielectric and the field electrode with the semiconductor layer;

forming a body region and a source region in the semiconductor layer;

forming a gate electrode that is dielectrically insulated from the body region by a gate dielectric;

forming a contact plug that extends from a surface of the semiconductor layer to the field electrode and adjoins the source region and the body region.

2. The method of claim 1, wherein forming the gate electrode comprises:

forming a first trench at least in the semiconductor layer;

forming the gate dielectric on sidewalls and a bottom of the first trench; and

forming the gate electrode on the gate dielectric in the first trench.

3. The method of claim 2, wherein forming the contact plug comprises:

forming a second trench in the semiconductor layer down to the field electrode; and

forming the contact plug in the second trench.

4. The method of claim 3, wherein forming the contact plug further comprises:

at least partially filling the second trench with a dielectric layer; and

removing the dielectric layer from the second trench before forming the contact plug.

5. The method of claim 3, wherein forming the contact plug comprises:

forming an electrically conducting barrier layer on a bottom and sidewalls of the second trench; and

forming an electrically conducting layer on the electrically conducting barrier.

6. The method of claim 5,

wherein at the barrier layer comprises at least one of titanium (Ti) and titanium nitride (TiN), and

wherein the electrically conducting layer comprises tungsten (W).

7. The method of claim 3, wherein forming the first trench and the second trench comprises forming the first trench and the second trench at the same time.

8. The method of claim 3, wherein forming the first trench and the second trench comprises forming the first trench and the second trench at different times.

9. The method of claim 4, wherein forming the gate dielectric and at least partially filling the second trench comprise forming the gate dielectric and at least partially filling the second trench at the same time.

10. The method of claim 1, further comprising:

forming a protection layer on the field electrode prior to epitaxially growing the semiconductor layer.

11. The method of claim 1, wherein forming the body region comprises at least partially forming the body region when epitaxially growing the semiconductor layer.

12. The method of claim 1, wherein forming the source region comprises forming the source region when epitaxially growing the semiconductor layer.

13. The method of claim 1, wherein forming the body region comprises introducing dopant atoms at least into the semiconductor layer via a surface of the semiconductor layer.

14. The method of claim 1, wherein forming the source region comprises introducing dopant atoms into the semiconductor layer via a surface of the semiconductor layer.

15. The method of claim 1, further comprising:

forming an insulation layer on the semiconductor layer; and

forming an electrode layer on the insulation such that the electrode layer is electrically connected to the contact plug.

16. The method of claim 15, wherein at least a part of the electrode layer and the contact plug are formed in the same process.

17. The method of claim 1, wherein the first trench is formed such that it overlaps the field electrode dielectric in a lateral direction of the semiconductor body.

18. The method of claim 1, wherein the semiconductor layer is epitaxially grown after providing the semiconductor body with both the trench and the at least one field electrode dielectric extending from the surface of the semiconductor body into the semiconductor body.

19. The method of claim 18, wherein epitaxially growing the semiconductor layer comprises epitaxially growing a semiconductor material on a mesa region of the semiconductor body that is adjacent to the trench such that the semiconductor material covers a region of the field electrode dielectric that extends to the surface of the semiconductor body.

20. The method of claim 18, wherein forming the contact plug comprises forming a trench in the semiconductor layer that exposes a top side of the field electrode and filling the trench with an electrically conductive material.