Controlling multiple facets of duty cycle response using a single motor integrated circuit pin

• US 10,243,490 B2
• Filed: 06/17/2016
• Issued: 03/26/2019
• Est. Priority Date: 06/17/2016
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Ogawa, Takashi, Kumazawa, Fumio
• Primary Examiner(s): Duda, Rina I
• Application Number:
  US15/186,078
• Publication Number:
  US 20170366116A1
• Time in Patent Office: 1,012 Days
• Field of Search: 318599, 318811, 388937, 388800, 388805, 388811, 388819
• CPC Class Codes: H02P 27/08 with pulse width modulation
• CPC Class Codes: H02P 6/14 Electronic commutators
• CPC Class Codes: H02P 6/24 Arrangements for stopping

Abstract

A system, in some embodiments, comprises: a motor; and control logic, coupled to the motor, to determine a duty keep status and a duty cycle threshold based on a received voltage, wherein the duty keep status indicates whether the system is to operate in a duty keep mode or a stop mode, wherein the duty cycle threshold indicates a minimum duty cycle for the motor if the system operates in said duty keep mode and indicates an input duty cycle threshold below which the control logic shuts off the motor if the system operates in the stop mode.

Claims

1. A system for controlling a motor, the system comprising:

a voltage divider circuit coupled to an input of a motor integrated circuit (IC);

a motor driver coupled to an output of the motor IC, the motor IC comprising;

a control logic configured to receive a voltage signal from the voltage divider circuit through an analog-to-digital converter (ADC);

a pulse-width-modulation (PWM) logic coupled with the control logic, the control logic configured to receive a PWM input signal; and

a motor controller coupled to an output of the control logic;

wherein the control logic is configured to generate a keep status and a duty cycle threshold based upon the voltage signal; and

wherein the keep status comprises one of a keep mode or a stop mode.

2. The system of claim 1, wherein the control logic is configured to send a stop signal if the control logic generates the stop mode and if the PWM input signal is less than the duty cycle threshold.

3. The system of claim 1, wherein the motor IC receives the voltage signal through a single input pin.

4. The system of claim 1, wherein the control logic comprises a set of voltage values and a corresponding set of duty cycle threshold values.

5. The system of claim 4, wherein a plurality of consecutive voltage values correspond to a single duty cycle threshold value.

6. The system of claim 4, wherein the set of voltage values and the set of duty cycle threshold values comprise a first portion corresponding to the keep mode and a second portion corresponding to the stop mode.

7. The system of claim 6, wherein the voltage signal corresponds with one of the first portion or the second portion.

8. A motor integrated circuit comprising:

an analog-to-digital converter (ADC) configured to receive a voltage signal from a voltage divider circuit;

a control logic coupled to the ADC, the control logic configured to receive a digital form of the voltage signal from the ADC; and

a pulse-width-modulation (PWM) logic coupled to the control logic, the control logic configured to receive a PWM input signal from the PWM logic;

wherein the control logic is configured to generate a keep status and a duty cycle threshold based upon the voltage signal, the keep status comprising one of a stop mode or a keep mode; and

wherein the control logic is configured to send a stop signal to a motor controller if the control logic generates the stop mode and if the PWM input signal is less than the duty cycle threshold.

9. The circuit of claim 8, wherein the control logic is configured to output a signal to maintain motor rotation if the control logic generates the keep mode.

10. The circuit of claim 8, wherein the control logic comprises a processor configured to receive the PWM input signal and the voltage signal.

11. The circuit of claim 8, wherein the circuit comprises the motor controller coupled to the control logic.

12. The circuit of claim 8, wherein the control logic comprises a set of voltage values and a set of duty cycle threshold values.

13. The system of claim 12, wherein a plurality of consecutive voltage values correspond to a single duty cycle threshold value.

14. The system of claim 12, wherein the set of voltage values and the set of duty cycle threshold values comprise a first portion corresponding to the keep mode and a second portion corresponding to the stop mode.

15. The system of claim 14, wherein the voltage signal corresponds with one of the first portion or the second portion.

16. A method of controlling a motor, the method comprising:

receiving, at a control logic, a voltage signal, the control logic comprising a set of voltage values and a set of duty cycle values;

calculating, using the control logic, a keep status and a duty cycle threshold based on the voltage signal, the set of voltage values, and the set of duty cycle values, wherein the keep status comprises one of a keep mode or a stop mode;

receiving, at the control logic, a pulse-width-modulation (PWM) input signal from a PWM logic;

determining, if the stop mode is calculated, using the control logic, whether the PWM input signal is less than the duty cycle threshold and sending, if the input signal is less than the duty cycle threshold, a stop signal to a motor controller coupled to the control logic; and

sending, if the keep mode is calculated, an output signal to the motor controller indicating that a motor is to continue rotating.

17. The method of claim 16, further comprising converting the voltage signal using an analog-to-digital converter.

18. The method of claim 16, wherein calculating comprises comparing the voltage signal to the set of voltage values comprised in the control logic.

19. The method of claim 16, wherein the set of voltage values corresponds to a set of duty cycle thresholds.

20. The method of claim 16, wherein the keep status and the duty cycle threshold are calculated without using the PWM input signal.