Bias control for stacked transistor configuration
First Claim
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1. A circuital arrangement comprising:
- i) an amplifier comprising;
stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;
an input port operatively connected to an input transistor of the stacked transistors;
an output port operatively connected to the drain terminal of the output transistor; and
a reference terminal operatively coupling the input transistor to a reference potential, wherein;
the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable supply voltage provided to the output transistor; and
ii) a gate bias circuit,wherein;
the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a bias voltage, the bias voltage comprising;
a) a dynamic bias voltage which is a function of the variable supply voltage when a voltage value of the variable supply voltage is above a predetermined value associated to the each transistor, the dynamic bias voltage configured to control the each transistor to operate in its saturation region of operation; and
b) a fixed bias voltage when the voltage value of the variable supply voltage is below the predetermined value associated to the each transistor, the fixed bias voltage configured to control the each transistor to operate in its triode region of operation in a top to down sequence so that the output transistor operates in its triode region of operation first, followed by a transistor of the one or more transistors of the second subset connected to the top transistor, and ending with a transistor of the one or more transistors of the second subset connected to the input transistor.
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Abstract
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed.
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Citations
33 Claims
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1. A circuital arrangement comprising:
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i) an amplifier comprising; stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors; an input port operatively connected to an input transistor of the stacked transistors; an output port operatively connected to the drain terminal of the output transistor; and a reference terminal operatively coupling the input transistor to a reference potential, wherein; the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable supply voltage provided to the output transistor; and ii) a gate bias circuit, wherein; the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a bias voltage, the bias voltage comprising; a) a dynamic bias voltage which is a function of the variable supply voltage when a voltage value of the variable supply voltage is above a predetermined value associated to the each transistor, the dynamic bias voltage configured to control the each transistor to operate in its saturation region of operation; and b) a fixed bias voltage when the voltage value of the variable supply voltage is below the predetermined value associated to the each transistor, the fixed bias voltage configured to control the each transistor to operate in its triode region of operation in a top to down sequence so that the output transistor operates in its triode region of operation first, followed by a transistor of the one or more transistors of the second subset connected to the top transistor, and ending with a transistor of the one or more transistors of the second subset connected to the input transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A circuital arrangement comprising:
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a plurality of stacked transistors comprising an input transistor and one or more cascode transistors; a biasing circuit configured to generate a plurality of gate bias voltages in correspondence of the one or more cascode transistors so as to selectively control each transistor of the one or more cascode transistors to operate in one of a saturation region of operation and a triode region of operation based on a voltage level of a varying supply voltage to the plurality of stacked transistors; and one or more gate capacitors connected between gate terminals of the one or more cascode transistors and a reference potential during operation in the saturation region and operation in the triode region, wherein each gate capacitor of the one or more gate capacitors is configured to allow a gate voltage at a gate terminal of a respective transistor of the one or more cascode transistors to vary along with a radio frequency (RF) voltage at a drain of the respective transistor. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A method for biasing an amplifier, the method comprising:
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providing an amplifier comprising stacked transistors in a cascode configuration, the stacked transistors comprising an input transistor and one or more cascode transistors; connecting gate capacitors between gate terminals of the one or more cascode transistors of the stacked transistors and a reference potential; applying a supply voltage to a drain of an output transistor of the stacked transistors; based on the applying, providing bias voltages to gate terminals of the stacked transistors; based on the providing, control the stacked transistors to operate in one of a saturation region of operation and a triode region of operation; and increasing or decreasing a voltage level of the supply voltage, wherein; increasing the voltage level comprises; based on the increasing, modifying the bias voltages to the gate terminals of the stacked transistors; and based on the modifying, controlling at least one transistor of the stacked transistors to switch operation from the triode region of operation to the saturation region of operation, and decreasing the voltage level comprises; based on the decreasing, modifying the bias voltages to the gate terminals of the stacked transistors; and based on the modifying, controlling at least one transistor of the stacked transistors to switch operation from the saturation region of operation to the triode region of operation, wherein each gate capacitor of the one or more gate capacitors is configured to allow a gate voltage at a gate terminal of a respective transistor of the one or more cascode transistors to vary along with a radio frequency (RF) voltage at a drain of the respective transistor. - View Dependent Claims (27, 28, 29, 30, 31)
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32. A circuital arrangement comprising:
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i) an amplifier comprising; stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors; an input port operatively connected to an input transistor of the stacked transistors; an output port operatively connected to the drain terminal of the output transistor; and a reference terminal operatively coupling the input transistor to a reference potential, wherein; the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable supply voltage provided to the output transistor; and ii) a gate bias circuit, wherein; the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a bias voltage, the bias voltage comprising; a) a dynamic bias voltage which is a function of the variable supply voltage when a voltage value of the variable supply voltage is above a predetermined value associated to the each transistor; and b) a fixed bias voltage when the voltage value of the variable supply voltage is below the predetermined value associated to the each transistor, the fixed bias voltage being generated via a resistor tree divider circuit based on a fixed reference voltage.
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33. A circuital arrangement comprising:
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i) an amplifier comprising; stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors; an input port operatively connected to an input transistor of the stacked transistors; an output port operatively connected to the drain terminal of the output transistor; and a reference terminal operatively coupling the input transistor to a reference potential, wherein; the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable supply voltage provided to the output transistor; and ii) a gate bias circuit, wherein; the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a bias voltage, the bias voltage comprising; a) a dynamic bias voltage which is a function of the variable supply voltage when a voltage value of the variable supply voltage is above a predetermined value associated to the each transistor; b) a fixed bias voltage when the voltage value of the variable supply voltage is below the predetermined value associated to the each transistor; and c) a gate bias selector circuit configured, for the each transistor of the one or more transistors of the second subset, to compare the dynamic bias voltage to the fixed bias voltage and to provide a larger of the dynamic bias voltage and the fixed bias voltage to the gate of the each transistor.
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Specification