Bias control for stacked transistor configuration

• US 10,243,519 B2
• Filed: 09/28/2016
• Issued: 03/26/2019
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Dykstra, Jeffrey A., Kovac, David
• Primary Examiner(s): Nguyen, Khanh V
• Assistant Examiner(s): Nguyen, Khiem
• Application Number:
  US15/279,274
• Publication Number:
  US 20170133989A1
• Time in Patent Office: 909 Days
• Field of Search: 330136, 330127, 330285, 330311
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/025 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 1/3205 in field-effect transistor amplifiers
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3282 Acting on the phase and the amplitude of the input signal
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/108 A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/129 there being a feedback over the complete amplifier
• CPC Class Codes: H03F 2200/15 the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/408 the output amplifying stage of an amplifier comprising three power stages
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/447 : the amplifier being protected to temperature influence
• CPC Class Codes: H03F 2200/451 : the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/468 : the temperature being sensed
• CPC Class Codes: H03F 2200/534 : Transformer coupled at the input of an amplifier
• CPC Class Codes: H03F 2200/537 : A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/541 : Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2200/61 : the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 2200/78 : A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2201/3215 : To increase the output power or efficiency
• CPC Class Codes: H03F 2201/3233 : Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H03F 2203/21127 : the input bias current of a power amplifier being controlled, e.g. by an active current source or a current mirror
• CPC Class Codes: H03F 2203/45366 : the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45544 : the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45638 : the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45731 : the LC comprising a transformer
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/211 : using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/213 : in integrated circuits
• CPC Class Codes: H03F 3/24 : of transmitter output stages
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages

Abstract

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage that varies according to a control voltage. The control voltage can be related to a desired output power of the amplifier and/or to an envelope signal of an input signal to the amplifier. Particular biasing for selectively controlling the stacked transistors to operate in either a saturation region or a triode region is also presented. Benefits of such controlling, including increased linear response of an output power of the amplifier, are also discussed.

Claims

1. A circuital arrangement comprising:

i) an amplifier comprising;

stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;

an input port operatively connected to an input transistor of the stacked transistors;

an output port operatively connected to the drain terminal of the output transistor; and

a reference terminal operatively coupling the input transistor to a reference potential, wherein;

the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable supply voltage provided to the output transistor; and

ii) a gate bias circuit,

wherein;

the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a bias voltage, the bias voltage comprising;

a) a dynamic bias voltage which is a function of the variable supply voltage when a voltage value of the variable supply voltage is above a predetermined value associated to the each transistor, the dynamic bias voltage configured to control the each transistor to operate in its saturation region of operation; and

b) a fixed bias voltage when the voltage value of the variable supply voltage is below the predetermined value associated to the each transistor, the fixed bias voltage configured to control the each transistor to operate in its triode region of operation in a top to down sequence so that the output transistor operates in its triode region of operation first, followed by a transistor of the one or more transistors of the second subset connected to the top transistor, and ending with a transistor of the one or more transistors of the second subset connected to the input transistor.

2. The circuital arrangement according to claim 1, wherein the dynamic bias voltage provides a substantially equal distribution of a voltage at the drain terminal of the output transistor across the stacked transistors.

3. The circuital arrangement according to claim 1 wherein:

the stacked transistors operate as a cascode configuration,

the dynamic bias voltage is configured to include the each transistor in a distribution of a voltage at the drain terminal of the output transistor across the stacked transistors, and

the fixed bias voltage is configured to exclude the each transistor from a distribution of the voltage at the drain of the output transistor across the stacked transistors.

4. The circuital arrangement according to claim 1, wherein the fixed bias voltage is generated via a resistor tree divider circuit based on a fixed reference voltage.

5. The circuital arrangement according to claim 1, wherein the gate bias circuit comprises a gate bias selector circuit configured, for the each transistor of the one or more transistors of the second subset, to compare the dynamic bias voltage to the fixed bias voltage and to provide a larger of the dynamic bias voltage and the fixed bias voltage to the gate of the each transistor.

6. The circuital arrangement according to claim 5, wherein the gate bias selector comprises:

a first PMOS transistor, wherein;

a source terminal of the first PMOS transistor is connected to a node carrying the dynamic bias voltage,

a gate terminal of the first PMOS transistor is connected to a node carrying the fixed bias voltage, and

a drain terminal of the first PMOS transistor is connected to the gate terminal of the each transistor, and

a second PMOS transistor, wherein;

a source terminal of the second PMOS transistor is connected to the node carrying the fixed bias voltage,

a gate terminal of the second PMOS transistor is connected to a node carrying the dynamic bias voltage, and

a drain terminal of the second PMOS transistor is connected to the gate terminal of the each transistor.

7. The circuital arrangement according to claim 6, wherein the first PMOS transistor and the second PMOS transistor each comprised an intrinsic PMOS transistor in parallel with a non-intrinsic PMOS transistor, wherein a size of the non-intrinsic PMOS transistor is substantially larger than a size of the intrinsic transistor.

8. The circuital arrangement according to claim 7, wherein gate terminals, source terminals and drain terminals of the intrinsic and the non-intrinsic PMOS transistors are connected.

9. The circuital arrangement according to claim 1, wherein an RF signal at the input port of the amplifier has a fixed amplitude and an output power of the amplifier is controlled by the variable supply voltage.

10. The circuital arrangement according to claim 9, wherein the variable supply voltage is provided by a low dropout regulator (LDO) controlled by a control voltage.

11. The circuital arrangement according to claim 10, wherein the amplifier is a GSM amplifier.

12. The circuital arrangement according to claim 10, wherein the control voltage is adapted to control the output power of the amplifier within a specified error based on a two-point calibration routine.

13. The circuital arrangement according to claim 12, wherein the two-point calibration routine comprises a first output power in correspondence of a first control voltage, and a second output power in correspondence of a second control voltage.

14. The circuital arrangement according to claim 13, wherein the specified error is according to a 3GPP specification for mobile broadband standard.

15. The circuital arrangement according to claim 1, further comprising one or more gate capacitors connected between the gate terminals of the one or more transistors of the second subset and the reference potential during operation in the saturation region and operation in the triode region.

16. The circuital arrangement according to claim 15, wherein capacitance values of the one or more gate capacitors are based on an operating frequency of an RF signal at the input port.

17. The circuital arrangement according to claim 1, wherein the variable supply voltage is based on an envelope signal of an RF signal at the input port.

18. The circuital arrangement according to claim 16, wherein the variable supply voltage is based on an envelope signal of an RF signal at the input port.

19. A circuital arrangement comprising:

a plurality of stacked transistors comprising an input transistor and one or more cascode transistors;

a biasing circuit configured to generate a plurality of gate bias voltages in correspondence of the one or more cascode transistors so as to selectively control each transistor of the one or more cascode transistors to operate in one of a saturation region of operation and a triode region of operation based on a voltage level of a varying supply voltage to the plurality of stacked transistors; and

one or more gate capacitors connected between gate terminals of the one or more cascode transistors and a reference potential during operation in the saturation region and operation in the triode region,

wherein each gate capacitor of the one or more gate capacitors is configured to allow a gate voltage at a gate terminal of a respective transistor of the one or more cascode transistors to vary along with a radio frequency (RF) voltage at a drain of the respective transistor.

20. The circuital arrangement according to claim 19, wherein:

the plurality of stacked transistors are configured to operate as an amplifier.

21. The circuital arrangement according to claim 20, wherein the amplifier is an RF amplifier.

22. The circuital arrangement according to claim 20, wherein the amplifier is a GSM amplifier, and wherein the varying supply voltage is provided by a low dropout regulator (LDO).

23. The circuital arrangement according to claim 20, wherein the amplifier is a linear amplifier configured to operate in an average power tracking mode, and wherein the varying supply voltage is provided by a DC-DC converter.

24. The circuital arrangement according to claim 19, wherein:

the plurality of gate bias voltages are fixed voltages based on a range of the voltage level of the varying supply voltage,

the plurality of gate bias voltages are adapted to maintain operation of the input transistor in its saturation region of operation for all values of the voltage level, and

the plurality of gate bias voltages are adapted to allow operation of a transistor of the plurality of stacked transistors different from the input transistor, to transition from a saturation region of operation to a triode region of operation, and vice versa, responsive to variations of the voltage level.

25. The circuital arrangement according to claim 19, wherein:

a gate bias voltage of the plurality of gate bias voltages to a transistor of the plurality of stacked transistors varies for values of the voltage level higher than a predetermined value, and is fixed for values of the voltage level lower than the predetermined value, and

the predetermined value is based on a position of said transistor within the plurality of stacked transistors.

26. A method for biasing an amplifier, the method comprising:

providing an amplifier comprising stacked transistors in a cascode configuration, the stacked transistors comprising an input transistor and one or more cascode transistors;

connecting gate capacitors between gate terminals of the one or more cascode transistors of the stacked transistors and a reference potential;

applying a supply voltage to a drain of an output transistor of the stacked transistors;

based on the applying, providing bias voltages to gate terminals of the stacked transistors;

based on the providing, control the stacked transistors to operate in one of a saturation region of operation and a triode region of operation; and

increasing or decreasing a voltage level of the supply voltage,

wherein;

increasing the voltage level comprises;

based on the increasing, modifying the bias voltages to the gate terminals of the stacked transistors; and

based on the modifying, controlling at least one transistor of the stacked transistors to switch operation from the triode region of operation to the saturation region of operation, and

decreasing the voltage level comprises;

based on the decreasing, modifying the bias voltages to the gate terminals of the stacked transistors; and

based on the modifying, controlling at least one transistor of the stacked transistors to switch operation from the saturation region of operation to the triode region of operation,

wherein each gate capacitor of the one or more gate capacitors is configured to allow a gate voltage at a gate terminal of a respective transistor of the one or more cascode transistors to vary along with a radio frequency (RF) voltage at a drain of the respective transistor.

27. The method according to claim 26, wherein modifying the bias voltages to the gate terminals of the stacked transistors responsive to the increasing of the voltage level comprises:

for the at least one transistor of the stacked transistors, switching a corresponding bias voltage from a fixed bias voltage independent from a variation of the supply voltage to a dynamic bias voltage that dynamically adjusts based on the variation of the supply voltage.

28. The method according to claim 27, wherein modifying the bias voltages to the gate terminals of the stacked transistors responsive to the decreasing of the voltage level comprises:

for the at least one transistor of the stacked transistors, switching a corresponding bias voltage from a dynamic bias voltage that dynamically adjusts based on the variation of the supply voltage to a fixed bias voltage independent from a variation of the supply voltage.

29. The method according to claim 28, wherein:

the supply voltage varies from a high voltage level to a low voltage level,

at the high voltage level of the supply voltage, all the stacked transistors operate in their respective saturation regions of operation, and

at the low voltage level of the supply voltage, all the stacked transistors at the exception of the input transistor to the amplifier operate in their respective triode regions of operation, the input transistor operating at its saturation region of operation.

30. The method according to claim 29, wherein modifying the bias voltages to the gate terminals of the stacked transistors responsive to the decreasing of the voltage level of the supply voltage, the voltage level of the supply voltage being at the high voltage level, comprises sequentially switching, from the output transistor of the stacked transistors to a bottom transistor of the stacked transistors connected to the input transistor, operation of each transistor of the stacked transistors from a saturation region of operation to a triode region of operation.

31. The method according to claim 30, wherein modifying the bias voltages to the gate terminals of the stacked transistors responsive to the increasing of the voltage level of the supply voltage, the voltage level of the supply voltage being at the low voltage level, comprises sequentially switching, from a bottom transistor of the stacked transistors connected to the input transistor to the output transistor of the stacked transistors, operation of each transistor of the stacked transistors from a triode region of operation to a saturation region of operation.

32. A circuital arrangement comprising:

i) an amplifier comprising;

stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;

an input port operatively connected to an input transistor of the stacked transistors;

an output port operatively connected to the drain terminal of the output transistor; and

a reference terminal operatively coupling the input transistor to a reference potential, wherein;

the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable supply voltage provided to the output transistor; and

ii) a gate bias circuit,

wherein;

the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a bias voltage, the bias voltage comprising;

a) a dynamic bias voltage which is a function of the variable supply voltage when a voltage value of the variable supply voltage is above a predetermined value associated to the each transistor; and

b) a fixed bias voltage when the voltage value of the variable supply voltage is below the predetermined value associated to the each transistor, the fixed bias voltage being generated via a resistor tree divider circuit based on a fixed reference voltage.

33. A circuital arrangement comprising:

i) an amplifier comprising;

stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;

an input port operatively connected to an input transistor of the stacked transistors;

an output port operatively connected to the drain terminal of the output transistor; and

a reference terminal operatively coupling the input transistor to a reference potential, wherein;

the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable supply voltage provided to the output transistor; and

ii) a gate bias circuit,

wherein;

the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a bias voltage, the bias voltage comprising;

a) a dynamic bias voltage which is a function of the variable supply voltage when a voltage value of the variable supply voltage is above a predetermined value associated to the each transistor;

b) a fixed bias voltage when the voltage value of the variable supply voltage is below the predetermined value associated to the each transistor; and

c) a gate bias selector circuit configured, for the each transistor of the one or more transistors of the second subset, to compare the dynamic bias voltage to the fixed bias voltage and to provide a larger of the dynamic bias voltage and the fixed bias voltage to the gate of the each transistor.