Error correction code (ECC) decoders sharing logic operations, memory controllers including the error correction code decoders, and methods of decoding error correction codes
First Claim
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1. An error correction code (ECC) decoder comprising:
- a finite state machine (FSM) controller configured to generate a first control signal and a second control signal each corresponding to a certain state of a plurality of states; and
a shared logic circuit configured to include a plurality of shared Galois field (GF) multipliers, a plurality of shared XOR arithmetic elements, and a plurality of shared multiplexers (MUXs), which are used for an operation selected between a syndrome operation, an error location polynomial operation, an error location operation, and an error correction operation, in response to the first and second control signals.
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Abstract
An error correction code (ECC) decoder includes a finite state machine (FSM) controller and a shared logic circuit. The FSM controller generates a first control signal and a second control signal each corresponding to a certain state. The shared logic circuit includes a plurality of shared Galois field (GF) multipliers, a plurality of shared XOR arithmetic elements, and a plurality of shared multiplexers (MUXs), which are used for an operation selected between a syndrome operation, an error location polynomial operation, an error location operation and an error correction operation, in response to the first and second control signals.
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Citations
18 Claims
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1. An error correction code (ECC) decoder comprising:
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a finite state machine (FSM) controller configured to generate a first control signal and a second control signal each corresponding to a certain state of a plurality of states; and a shared logic circuit configured to include a plurality of shared Galois field (GF) multipliers, a plurality of shared XOR arithmetic elements, and a plurality of shared multiplexers (MUXs), which are used for an operation selected between a syndrome operation, an error location polynomial operation, an error location operation, and an error correction operation, in response to the first and second control signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of decoding error correction codes, the method comprising:
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providing a shared logic circuit including a plurality of shared Galois field (GF) multipliers, a plurality of shared XOR arithmetic elements, and a plurality of shared multiplexers (MUXs); providing a finite state machine (FSM) controller generating a first control signal and a second control signal each corresponding to a certain state of a plurality of states; and driving the shared logic circuit including the plurality of shared GF multipliers, the plurality of shared XOR arithmetic elements and the plurality of shared MUXs to perform an operation selected between a syndrome operation, an error location polynomial operation, an error location operation, and an error correction operation, in response to the first and second control signals. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification