Integrated mixed-signal ASIC with ADC and DSP
First Claim
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1. An integrated analog to digital converting RF receiver implemented in a satellite, comprising:
- a plurality of radiation tolerant high speed analog to digital converters (ADCs), which each receive an RF signal and output a sampled digital signal;
a plurality of radiation tolerant digital outputs; and
one or more radiation tolerant digital signal processing (DSP) cores, which each process data from at least one radiation tolerant high speed ADC and output the processed data on one or more of the radiation tolerant digital outputs;
wherein one or more of the radiation tolerant high speed ADCs, the one or more of the radiation tolerant digital outputs, and/or the one or more radiation tolerant DSP cores have been determined, by testing, to be radiation tolerant and have a heavy ion cross section less than or equal to 10−
4 cm2 (square centimeters) at a linear energy transfer greater than or equal to 37 MeV cm2/mg (mega-electronVolts-square centimeters per milligram).
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Abstract
An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.
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Citations
27 Claims
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1. An integrated analog to digital converting RF receiver implemented in a satellite, comprising:
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a plurality of radiation tolerant high speed analog to digital converters (ADCs), which each receive an RF signal and output a sampled digital signal; a plurality of radiation tolerant digital outputs; and one or more radiation tolerant digital signal processing (DSP) cores, which each process data from at least one radiation tolerant high speed ADC and output the processed data on one or more of the radiation tolerant digital outputs; wherein one or more of the radiation tolerant high speed ADCs, the one or more of the radiation tolerant digital outputs, and/or the one or more radiation tolerant DSP cores have been determined, by testing, to be radiation tolerant and have a heavy ion cross section less than or equal to 10−
4 cm2 (square centimeters) at a linear energy transfer greater than or equal to 37 MeV cm2/mg (mega-electronVolts-square centimeters per milligram). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. An integrated analog to digital converting RF receiver implemented in a satellite, comprising:
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a plurality of radiation tolerant high speed analog to digital converters (ADCs), which each receive an RF signal and output a sampled digital signal; a plurality of radiation tolerant digital outputs; and one or more radiation tolerant reconfigurable digital signal processing (DSP) cores, which each DSP core processes data from at least one radiation tolerant high speed ADC and output the processed data on one or more of the radiation tolerant digital outputs; wherein the RF receiver is implemented in the satellite and one or more of the radiation tolerant high speed ADCs, the one or more of the radiation tolerant digital outputs, and/or the one or more radiation tolerant configurable DSP cores are radiation hard by design (RHBD) or radiation hard by process (RHBP) to mitigate at least one of single event latchup (SEL), single event upset (SEU), single event transient (SET), and single event functional interrupt (SEFI) radiation effects; and wherein the plurality of radiation tolerant high speed ADCs, the plurality of radiation tolerant digital outputs, and the one or more radiation tolerant reconfigurable DSP cores are integrated on a single monolithic silicon device. - View Dependent Claims (22, 23, 24, 25)
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26. An integrated analog to digital converting RF receiver implemented in a satellite, comprising:
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a plurality of radiation tolerant high speed analog to digital converters (ADCs), which each receive an RF signal and output a sampled digital signal; a plurality of radiation tolerant digital outputs; and one or more radiation tolerant reconfigurable digital signal processing (DSP) cores, which each process data from at least one radiation tolerant high speed ADC and output the processed data on one or more of the radiation tolerant digital outputs; wherein the plurality of radiation tolerant high speed ADCs, the plurality of radiation tolerant digital outputs, and the one or more radiation tolerant reconfigurable DSP cores are integrated and contained on one die or a plurality of die all located in a single package, and at least one of the radiation tolerant high speed ADCs, the plurality of radiation tolerant digital outputs, and/or the one or more radiation tolerant reconfigurable DSP cores have been determined, by testing or analysis, to be radiation tolerant. - View Dependent Claims (27)
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Specification