Method and apparatus for high speed chip-to-chip communications

• US 10,243,765 B2
• Filed: 06/06/2017
• Issued: 03/26/2019
• Est. Priority Date: 10/22/2014
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin, Ulrich, Roger
• Primary Examiner(s): Burd, Kevin M
• Application Number:
  US15/615,262
• Publication Number:
  US 20170272285A1
• Time in Patent Office: 658 Days
• Field of Search: 375376, 375373, 375371, 375354
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828

Abstract

Described herein are systems and methods of receiving first and second input signals at a first two-input comparator, responsively generating a first subchannel output, receiving third and fourth input signals at a second two-input comparator, responsively generating a second subchannel output, receiving the first, second, third, and fourth input signals at a third multi-input comparator, responsively generating a third subchannel output representing a comparison of an average of the first and second input signals to an average of the third and fourth input signals, configuring a first data detector connected to the second subchannel output and a second data detector connected to the third subchannel output according to a legacy mode of operation and a P4 mode of operation.

Claims

1. An apparatus comprising:

a plurality of multi-input comparators (MICs) connected to wires of a multi-wire bus having at least three wires, each MIC configured to detect a corresponding sub-channel of a plurality of mutually orthogonal sub-channels, the plurality of MICs comprising;

a MIC connected to all the wires of the multi-wire bus and configured to receive a set of signals in a signaling interval, the received set of signals corresponding to symbols of a codeword of a vector signaling code, the MIC configured to generate a detected sub-channel output in a first mode of operation, and powered down in a second mode of operation; and

two MICs, each MIC selectably configured to (i) form a comparison between a respective two wires in the first mode of operation, the respective two wires carrying a respective set of two signals representing symbols of the codeword and to responsively generate a respective detected sub-channel output, or (ii) to form a comparison between a respective differential signal received on a respective two wires in the second mode of operation and to produce a corresponding detected output; and

a controller configured to selectably configure the plurality of MICs to operate in the first or the second mode of operation.

2. The apparatus of claim 1, wherein the detected output of at least one of the two MICs is a data signal in the second mode of operation.

3. The apparatus of claim 1, wherein the detected output of one of the two MICs is a clock signal in the second mode of operation.

4. The apparatus of claim 1, further comprising a clock recovery circuit configured to detect a clock signal based on detected sub-channel outputs in the first mode of operation.

5. The apparatus of claim 4, wherein the clock recovery circuit is an edge-based clock recovery circuit configured to detect the clock signal based at least in part on transitions in the detected sub-channel outputs.

6. The apparatus of claim 1, wherein the multi-wire bus comprises four wires, and wherein the plurality of MICs comprises three MICs.

7. The apparatus of claim 1, wherein each MIC in the two MICs has equal scaling factors for each received signal.

8. The apparatus of claim 1, wherein each detected sub-channel output corresponds to an analog linear combination of symbols of the codeword.

9. The apparatus of claim 8, further comprising a plurality of slicers, each slicer configured to receive a corresponding analog linear combination and to responsively generate an output bit of a set of output bits.

10. The apparatus of claim 1, wherein the respective detected sub-channel output generated by one of the two MICs corresponds to a clock signal in the first mode of operation.

11. A method comprising:

receiving a set of signals in a signaling interval at a plurality of multi-input comparators (MICs), the set of signals corresponding to symbols of a codeword of a vector signaling code and received via wires of a multi-wire bus;

generating, using a MIC connected to all the wires of the multi-wire bus, a detected sub-channel output in a first mode of operation, and powering off the MIC connected to all the wires of the multi-wire bus in a second mode of operation;

selectably configuring two MICs, each MIC selectably configured to (i) generate a respective detected sub-channel output based on a respective set of two signals representing symbols of the codeword received via a respective set of two wires of the multi-wire bus, or (ii) to generate a respective detected output based on a respective differential signal received via a respective two wires of the multi-wire bus; and

selectably configuring the plurality of MICs to operate in the first or the second mode of operation.

12. The method of claim 11, wherein the detected output at least one of the two MICs is a data signal in the second mode of operation.

13. The method of claim 11, wherein the detected output of one of the two MICs is a clock signal in the second mode of operation.

14. The method of claim 11, further comprising detecting a clock signal based on detected sub-channel outputs in the first mode of operation.

15. The method of claim 14, wherein detecting the clock signal comprises detecting transitions in the detected sub-channel outputs.

16. The method of claim 11, wherein the signals are received on four wires of the multi-wire bus, at three MICs.

17. The method of claim 11, wherein each MIC in the at least two MICs has equal scaling factors for each received signal.

18. The method of claim 11, wherein each detected sub-channel output corresponds to an analog linear combination of symbols of the codeword.

19. The method of claim 18, further comprising slicing each analog linear combination to generate a set of output bits.

20. The method of claim 11, wherein the respective detected sub-channel output generated by one of the two MICs corresponds to a clock signal in the first mode of operation.