Method and apparatus for high speed chip-to-chip communications
First Claim
1. An apparatus comprising:
- a plurality of multi-input comparators (MICs) connected to wires of a multi-wire bus having at least three wires, each MIC configured to detect a corresponding sub-channel of a plurality of mutually orthogonal sub-channels, the plurality of MICs comprising;
a MIC connected to all the wires of the multi-wire bus and configured to receive a set of signals in a signaling interval, the received set of signals corresponding to symbols of a codeword of a vector signaling code, the MIC configured to generate a detected sub-channel output in a first mode of operation, and powered down in a second mode of operation; and
two MICs, each MIC selectably configured to (i) form a comparison between a respective two wires in the first mode of operation, the respective two wires carrying a respective set of two signals representing symbols of the codeword and to responsively generate a respective detected sub-channel output, or (ii) to form a comparison between a respective differential signal received on a respective two wires in the second mode of operation and to produce a corresponding detected output; and
a controller configured to selectably configure the plurality of MICs to operate in the first or the second mode of operation.
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Abstract
Described herein are systems and methods of receiving first and second input signals at a first two-input comparator, responsively generating a first subchannel output, receiving third and fourth input signals at a second two-input comparator, responsively generating a second subchannel output, receiving the first, second, third, and fourth input signals at a third multi-input comparator, responsively generating a third subchannel output representing a comparison of an average of the first and second input signals to an average of the third and fourth input signals, configuring a first data detector connected to the second subchannel output and a second data detector connected to the third subchannel output according to a legacy mode of operation and a P4 mode of operation.
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Citations
20 Claims
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1. An apparatus comprising:
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a plurality of multi-input comparators (MICs) connected to wires of a multi-wire bus having at least three wires, each MIC configured to detect a corresponding sub-channel of a plurality of mutually orthogonal sub-channels, the plurality of MICs comprising; a MIC connected to all the wires of the multi-wire bus and configured to receive a set of signals in a signaling interval, the received set of signals corresponding to symbols of a codeword of a vector signaling code, the MIC configured to generate a detected sub-channel output in a first mode of operation, and powered down in a second mode of operation; and two MICs, each MIC selectably configured to (i) form a comparison between a respective two wires in the first mode of operation, the respective two wires carrying a respective set of two signals representing symbols of the codeword and to responsively generate a respective detected sub-channel output, or (ii) to form a comparison between a respective differential signal received on a respective two wires in the second mode of operation and to produce a corresponding detected output; and a controller configured to selectably configure the plurality of MICs to operate in the first or the second mode of operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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receiving a set of signals in a signaling interval at a plurality of multi-input comparators (MICs), the set of signals corresponding to symbols of a codeword of a vector signaling code and received via wires of a multi-wire bus; generating, using a MIC connected to all the wires of the multi-wire bus, a detected sub-channel output in a first mode of operation, and powering off the MIC connected to all the wires of the multi-wire bus in a second mode of operation; selectably configuring two MICs, each MIC selectably configured to (i) generate a respective detected sub-channel output based on a respective set of two signals representing symbols of the codeword received via a respective set of two wires of the multi-wire bus, or (ii) to generate a respective detected output based on a respective differential signal received via a respective two wires of the multi-wire bus; and selectably configuring the plurality of MICs to operate in the first or the second mode of operation. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification