MEMS device and method for manufacturing a MEMS device

• US 10,246,325 B2
• Filed: 08/21/2015
• Issued: 04/02/2019
• Est. Priority Date: 09/03/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kolb, Stefan, Meiser, Andreas, Schloesser, Till, Werner, Wolfgang
• Primary Examiner(s): Gondarenko, Natalia A
• Application Number:
  US14/832,001
• Publication Number:
  US 20160060105A1
• Time in Patent Office: 1,320 Days
• Field of Search: 257415, 257417, 257470, 257E29324, 257E29347, 257E21231, 257E21502, 257E21002, 438 51, 438 50, 438 54, 438 57, 438482, 438 19, 438760, 438 29, 438 46, 438478
• CPC Class Codes: B81C 1/00182 Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers

Abstract

A method for producing a MEMS device comprises forming a semiconductor layer stack, the semiconductor layer stack comprising at least a first monocrystalline semiconductor layer, a second monocrystalline semiconductor layer and a third monocrystalline semiconductor layer, the second monocrystalline semiconductor layer formed between the first and third monocrystalline semiconductor layers. A semiconductor material of the second monocrystalline semiconductor layer is different from semiconductor materials of the first and third monocrystalline semiconductor layers. After forming the semiconductor layer stack, at least a portion of each of the first and third monocrystalline semiconductor layers is concurrently etched.

Claims

1. A method for producing a MEMS device, comprising:

forming a semiconductor layer stack, the semiconductor layer stack comprising at least a first monocrystalline semiconductor layer, a second monocrystalline semiconductor layer, a third monocrystalline semiconductor layer, a fourth monocrystalline semiconductor layer, and a fifth monocrystalline semiconductor layer, the second monocrystalline semiconductor layer formed between the first and third monocrystalline semiconductor layers, the first monocrystalline semiconductor layer being formed above the fourth monocrystalline semiconductor layer and the fifth monocrystalline semiconductor layer being formed above the third monocrystalline semiconductor layer, wherein a semiconductor material of the second monocrystalline semiconductor layer is different from semiconductor materials of the first and third monocrystalline semiconductor layers, at least one layer of the semiconductor layer stack includes a compound semiconductor material and at least one layer of the semiconductor layer stack includes a non-compound semiconductor material, and adjacent layers of the first, the second, and the third monocrystalline semiconductor layers have mutual different doping types;

etching the first, the second, the third, and the fifth monocrystalline semiconductor layers to form channels extending from the fifth monocrystalline semiconductor layer to the first monocrystalline semiconductor layer and terminating within the first monocrystalline semiconductor layer;

etching, via the channels, the first and the third monocrystalline semiconductor layers, wherein a movable first portion of the second monocrystalline semiconductor layer forming a movable MEMS element is released by removing a first portion of the first monocrystalline semiconductor layer and a first portion of the third monocrystalline semiconductor layer, second and third portions of the first monocrystalline semiconductor layer remaining below respective second and third portions of the second monocrystalline semiconductor layer, and second and third portions of the third monocrystalline semiconductor layer remaining above the second and the third portions of the second monocrystalline semiconductor layer, the movable first portion of the second monocrystalline semiconductor layer being separated laterally by gaps defined by the channels and vertically by gaps defined by the removed first portion of the first monocrystalline semiconductor layer between the fourth monocrystalline semiconductor layer and the second monocrystalline semiconductor layer and the removed first portion of the third monocrystalline semiconductor layer between the second monocrystalline semiconductor layer and the fifth monocrystalline semiconductor layer; and

providing a monocrystalline semiconductor material in a portion of the channels within the fifth monocrystalline semiconductor layer to seal the channels.

2. The method according to claim 1, wherein the first, second and third monocrystalline semiconductor layers are epitaxial grown monocrystalline semiconductor layers.

3. The method according to claim 1, wherein the second monocrystalline semiconductor layer and the fourth and fifth semiconductor layers comprise a same semiconductor material.

4. The method according to claim 3, wherein the first and third monocrystalline semiconductor layers comprise a semiconductor material different from a semiconductor material of the second monocrystalline semiconductor layer and the fourth and fifth semiconductor layers.

5. The method according to claim 1, wherein a semiconductor crystal structure of the first and third monocrystalline semiconductor layers have a first lattice constant which is different to a second lattice constant of a semiconductor crystal structure of the second monocrystalline semiconductor layer, wherein a difference of the first and second lattice constants is not greater than 10%.

6. The method according to claim 5, wherein the first and third monocrystalline semiconductor layers comprise the compound semiconductor material.

7. The method according to claim 6, wherein a crystal structure of the second monocrystalline semiconductor layer is formed by a lattice arrangement of first atoms and a crystal structure of the compound semiconductor material is formed by a lattice arrangement of the first atoms and second atoms.

8. The method according to claim 7, wherein the first and second atoms are chemical elements of a same group within a periodic table of chemical elements.

9. The method according to claim 1, wherein the etching of the first portion of each of the first and the third monocrystalline semiconductor layers removes at least a portion of the first and the third monocrystalline semiconductor layers below and above a first portion of the second monocrystalline semiconductor layer, respectively, while the first and the third monocrystalline semiconductor layers remain below and above a second portion of the second monocrystalline semiconductor layer, respectively, and wherein the channels separate the first portion of the second monocrystalline semiconductor layer into the movable portion of the second monocrystalline semiconductor layer and a non-movable portion of the first portion of the second monocrystalline semiconductor layer.

10. The method according to claim 9, wherein no etch stop is provided lateral to the first and third monocrystalline semiconductor layers to stop the etching of at least a portion of the first and third monocrystalline semiconductor layers.

11. The method according to claim 1, wherein a lateral etch stop is provided lateral to at least one of the first and third monocrystalline semiconductor layers to stop the etching of at least a portion of the first and third monocrystalline semiconductor layers.

12. The method according to claim 1, wherein an etchant is provided via the channels.

13. The method according to claim 12, further comprising at least partially filling the channels with monocrystalline semiconductor material prior to the etching of the first portion of the first monocrystalline semiconductor layer and the first portion of the third monocrystalline semiconductor layer.

14. The method according to claim 13, wherein the monocrystalline semiconductor material in the channels comprises a same material as the material of at least one of the first and third monocrystalline semiconductor layers.

15. The method according to claim 1, wherein the second monocrystalline semiconductor layer is structured prior to the etching of the first portions of the first and the third monocrystalline semiconductor layers such that gap portions at least partially surrounding the movable portion of the second monocrystalline layer are formed in the second monocrystalline semiconductor layer.

16. The method according to claim 15, wherein forming the semiconductor stack comprises:

epitaxial growing the second monocrystalline semiconductor layer on the first monocrystalline semiconductor layer;

structuring the second monocrystalline semiconductor layer such that gap portions are formed by removing at least a portion of the second monocrystalline semiconductor layer;

providing an epitaxial grow process to form the third monocrystalline semiconductor layer above the second monocrystalline semiconductor layer and to fill the gap portions with epitaxial grown semiconductor material;

etching at least a portion of each of the first and third monocrystalline semiconductor layers and at least a portion of the epitaxial grown semiconductor material in the gap portions.

17. The method according to claim 12, wherein the channels at least partially surround the movable portion of the second monocrystalline semiconductor layer.

18. The method according to claim 1, wherein the sealed fifth monocrystalline semiconductor layer forms a cover of the MEMS device.

19. The method according to claim 1, further comprising:

forming a sixth monocrystalline semiconductor layer, a seventh monocrystalline semiconductor layer and an eighth monocrystalline semiconductor layer,

wherein the sixth monocrystalline semiconductor layer is formed above the fifth monocrystalline semiconductor layer and wherein the seventh monocrystalline semiconductor layer is formed between the sixth monocrystalline semiconductor layer and the eighth monocrystalline semiconductor layer, and

wherein at least a portion of the sixth and eighth monocrystalline semiconductor layers is etched to release a further movable MEMS element.

20. The method according to claim 13, wherein the monocrystalline semiconductor material that at least partially fills the channels is a portion of the first monocrystalline semiconductor layer.

21. The method according to claim 1, wherein the first monocrystalline semiconductor layer is only partially etched such that the channels terminate within the first monocrystalline semiconductor layer.

22. The method according to claim 1, wherein the channels have a channel width and the first monocrystalline semiconductor layer has a layer thickness, wherein a ratio of the channel width to the layer thickness is selected to control the etching of the first and the third monocrystalline semiconductor layers.

23. The method according to claim 1, wherein the etching of the first and the third monocrystalline semiconductor layers via the channels removes greater amounts of the second and third portions of the third monocrystalline semiconductor layer than amounts of the second and third portions of the first monocrystalline semiconductor layer.

24. The method according to claim 1, wherein the etching of the first and the third monocrystalline semiconductor layers comprises providing an etchant via the channels in a direction from the fifth monocrystalline semiconductor layer to the first monocrystalline semiconductor layer to remove greater amounts of the second and third portions of the third monocrystalline semiconductor layer than amounts of the second and third portions of the first monocrystalline semiconductor layer.

25. The method according to claim 1, wherein:

the second and the third portions of the first monocrystalline semiconductor layer, and the second and the third portions of the second monocrystalline semiconductor layer are laterally disposed with respect to the movable MEMS element such that the movable MEMS element is positioned between the second and the third portions of the first monocrystalline semiconductor layer and the second and the third portions of the second monocrystalline semiconductor layer; and

the channels separate the movable MEMS from the second and the third portions of the first monocrystalline semiconductor layer and the second and the third portions of the second monocrystalline semiconductor layer.

26. The method according to claim 1, wherein the first and third monocrystalline semiconductor layers comprise the compound semiconductor material and the second monocrystalline semiconductor layer comprises the non-compound semiconductor material.

27. The method according to claim 1, wherein the compound semiconductor material comprises two or more different chemical elements and the non-compound semiconductor material comprises a single chemical element.

28. The method according to claim 1, wherein the first and the third monocrystalline semiconductor layers are p-doped, and the second monocrystalline semiconductor layer is n-doped.

29. The method according to claim 1, wherein the first and the third monocrystalline semiconductor layers are n-doped, and the second monocrystalline semiconductor layer is p-doped.