Semiconductor device including clock generating circuit and channel management circuit
First Claim
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1. A semiconductor device, comprising:
- a first clock generating circuit including a first control circuit and a first clock gating circuit;
a first channel management circuit which communicates with the first clock generating circuit according to a full handshake method;
a second clock generating circuit including a second control circuit and a second clock gating circuit; and
a second channel management circuit which communicates with the second clock generating circuit according to the full handshake method,wherein the first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock,wherein the first channel management circuit transmits a second clock request signal to the first clock generating circuit in response to a first clock request signal, and the first clock generating circuit transmits a first clock acknowledgement signal to the first channel management circuit in response to the second clock request signal,wherein the second channel management circuit transmits a fourth clock request signal to the second clock generating circuit in response to a third clock request signal, and the second clock generating circuit transmits a second clock acknowledgement signal to the second channel management circuit in response to the fourth clock request signal.
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Abstract
A semiconductor device includes a first clock generating circuit including a first control circuit and a first clock gating circuit, a first channel management circuit which communicates with the first clock generating circuit according to a full handshake method, a second clock generating circuit including a second control circuit and a second clock gating circuit, and a second channel management circuit which communicates with the second clock generating circuit according to the full handshake method. The first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock.
65 Citations
15 Claims
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1. A semiconductor device, comprising:
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a first clock generating circuit including a first control circuit and a first clock gating circuit; a first channel management circuit which communicates with the first clock generating circuit according to a full handshake method; a second clock generating circuit including a second control circuit and a second clock gating circuit; and a second channel management circuit which communicates with the second clock generating circuit according to the full handshake method, wherein the first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock, wherein the first channel management circuit transmits a second clock request signal to the first clock generating circuit in response to a first clock request signal, and the first clock generating circuit transmits a first clock acknowledgement signal to the first channel management circuit in response to the second clock request signal, wherein the second channel management circuit transmits a fourth clock request signal to the second clock generating circuit in response to a third clock request signal, and the second clock generating circuit transmits a second clock acknowledgement signal to the second channel management circuit in response to the fourth clock request signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device, comprising:
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a first clock generating circuit including a first control circuit and a first clock gating circuit; a first channel management circuit which communicates with the first clock generating circuit according to a full handshake method; and a second clock generating circuit including a second control circuit and a second clock gating circuit, wherein the second clock generating circuit communicates with the first channel management circuit according to the full handshake method, and the first clock gating circuit outputs a first clock, and the second clock gating circuit outputs a second clock different from the first clock, wherein the first channel management circuit transmits a first clock request signal to the first clock generating circuit, and a second clock request signal to the second clock generating circuit, wherein the first clock generating circuit transmits a first clock acknowledgement signal to the first channel management circuit in response to the first clock request signal, wherein the second clock generating circuit transmits a second clock acknowledgement signal to the first channel management circuit in response to the second clock request signal. - View Dependent Claims (11)
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12. A semiconductor device, comprising:
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a first clock generating circuit including a first control circuit and a first clock gating circuit; a first channel management circuit which communicates with the first clock generating circuit according to a full handshake method; and a second channel management circuit which communicates with the first clock generating circuit according to the full handshake method, wherein the first channel management circuit transmits a first clock request signal to the first clock generating circuit, and the second channel management circuit transmits a second clock request signal to the first clock generating circuit, wherein the first clock generating circuit transmits a first clock acknowledgment signal to the first channel management circuit in response to the first clock request signal, and transmits a second clock acknowledgment signal to the second channel management circuit in response to the second clock request signal. - View Dependent Claims (13, 14, 15)
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Specification