Enabling a non-core domain to control memory bandwidth in a processor
First Claim
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1. A mobile device comprising:
- a processor;
memory coupled to the processor;
storage coupled to the processor; and
a display coupled to the processor;
wherein the processor comprises;
a plurality of cores of the processor, a first core of the plurality of cores to operate at a first voltage and a second core of the plurality of cores to operate at a second voltage, the second voltage independent of the first voltage;
the first core of the plurality of cores to be associated with a first frequency and the second core of the plurality of cores to be associated with a second frequency, wherein the first and second frequencies may be different from each other;
a graphics unit of the processor, wherein a driver of the graphics unit is to control execution on the graphics unit;
an interconnect of the processor to couple the first core of the plurality of cores, the second core of the plurality of cores and the graphics unit to a memory external to the processor; and
a power controller to control a frequency of the interconnect based at least in part on a frequency of the graphics unit, wherein the graphics unit is operable at a first plurality of frequencies and the interconnect is operable at a second plurality of frequencies, and the power controller is to update the frequency of the interconnect to another one of the second plurality of frequencies based at least in part on the frequency of the graphics unit.
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Abstract
In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
125 Citations
20 Claims
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1. A mobile device comprising:
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a processor; memory coupled to the processor; storage coupled to the processor; and a display coupled to the processor; wherein the processor comprises; a plurality of cores of the processor, a first core of the plurality of cores to operate at a first voltage and a second core of the plurality of cores to operate at a second voltage, the second voltage independent of the first voltage; the first core of the plurality of cores to be associated with a first frequency and the second core of the plurality of cores to be associated with a second frequency, wherein the first and second frequencies may be different from each other; a graphics unit of the processor, wherein a driver of the graphics unit is to control execution on the graphics unit; an interconnect of the processor to couple the first core of the plurality of cores, the second core of the plurality of cores and the graphics unit to a memory external to the processor; and a power controller to control a frequency of the interconnect based at least in part on a frequency of the graphics unit, wherein the graphics unit is operable at a first plurality of frequencies and the interconnect is operable at a second plurality of frequencies, and the power controller is to update the frequency of the interconnect to another one of the second plurality of frequencies based at least in part on the frequency of the graphics unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computing system comprising:
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a processor; memory coupled to the processor; and storage coupled to the processor; wherein the processor comprises; a plurality of cores of the processor, a first core of the plurality of cores to operate at a first voltage and a second core of the plurality of cores to operate at a second voltage, the second voltage independent of the first voltage; the first core of the plurality of cores to be associated with a first frequency and the second core of the plurality of cores to be associated with a second frequency, wherein the first and second frequencies may be different from each other; a graphics unit of the processor, wherein a driver of the graphics unit is to control execution on the graphics unit; an interconnect of the processor to couple the first core of the plurality of cores, the second core of the plurality of cores and the graphics unit to a memory external to the processor; and a power controller to control a frequency of the interconnect based at least in part on a frequency of the graphics unit, wherein the graphics unit is operable at a first plurality of frequencies and the interconnect is operable at a second plurality of frequencies, and the power controller is to update the frequency of the interconnect to another one of the second plurality of frequencies based at least in part on the frequency of the graphics unit. - View Dependent Claims (12, 13, 14, 15)
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16. An apparatus comprising:
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processor means for executing instructions; memory means for storing first information, the memory means coupled to the processor means; storage means for storing at least second information, the storage means coupled to the processor means; and display means for displaying information, the display means coupled to the processor means, wherein the processor means comprises; a plurality of core means, a first core means of the plurality of core means for operating at a first voltage and a second core means of the plurality of core means for operating at a second voltage, the second voltage independent of the first voltage; the first core means of the plurality of core means to be associated with a first frequency and the second core means of the plurality of core means to be associated with a second frequency, wherein the first and second frequencies may be different from each other; a graphics means, wherein a driver means of the graphics means for controlling execution on the graphics means; an interconnect means for coupling the first core means, the second core means and the graphics means to a memory external to the apparatus; and a power control means for controlling a frequency of the interconnect means based at least in part on a frequency of the graphics means, wherein the graphics means is operable at a first plurality of frequencies and the interconnect means is operable at a second plurality of frequencies, and the power control means for updating the frequency of the interconnect means to another one of the second plurality of frequencies based at least in part on the frequency of the graphics means. - View Dependent Claims (17, 18, 19, 20)
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Specification
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Current AssigneeDaedalus Prime LLC (Daedalus Group LLC)
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Original AssigneeIntel Corporation
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InventorsAnanthakrishnan, Avinash N., Sodhi, Inder M., Rotem, Efraim, Rajwan, Doron, Weissmann, Eliezer, Wells, Ryan
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Primary Examiner(s)Phan, Raymond N
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Application NumberUS15/381,241Publication NumberTime in Patent Office837 DaysField of Search713300-340US Class CurrentCPC Class CodesG06F 1/3203 Power management, i.e. even...G06F 1/324 by lowering clock frequencyG06F 1/3293 by switching to a less powe...G06F 1/3296 by lowering the supply or o...G06F 13/4068 Electrical couplingG06F 13/4282 on a serial bus, e.g. I2C b...G11C 7/22 Read-write [R-W] timing or ...Y02D 10/00 Energy efficient computing,...
