System and method for power management

• US 10,248,183 B2
• Filed: 12/06/2016
• Issued: 04/02/2019
• Est. Priority Date: 01/04/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chin, Jennifer, Lim, Su Wei, Teoh, Poh Thiam, Song, Ting Lok, E, Sun Zheng, Gan, Say Cheong, Lim, Sujea, Lim, Ming Yi
• Primary Examiner(s): Yen, Paul
• Application Number:
  US15/370,507
• Publication Number:
  US 20170083079A1
• Time in Patent Office: 847 Days
• Field of Search: None
• CPC Class Codes: G06F 1/1626 with a single-body enclosure integrating a flat display, e.g. Personal Digital Assistants [PDAs]
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3218 of display devices
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Particular embodiments described herein can offer a method for managing power for at least one processor that includes evaluating a plurality of ports associated with an electronic device; determining that a particular pin associated with at least one of the ports is not receiving a signal; disabling a squelch function associated with the electronic device; and gating power associated with a physical layer (PHY) of the electronic device.

Claims

1. A system, comprising:

a processor; and

a memory to store instructions executable by the processor to perform operations comprising;

identifying a power management event (PME) timeout;

directing a receiver in a physical layer (PHY) to turn off;

transitioning from a powered-on link state to a recovery state; and

resuming a detection state associated with a predetermined timeout associated with failing to receive a sequence from the electronic device, wherein the detection state is resumed before clearing a runtime-entry configuration bit for the electronic device.

2. The system of claim 1, wherein incoming data is cut off from the electronic device in response to the PHY being turned off.

3. The system of claim 1, wherein the detection state is resumed before indicating a layer 2/layer 3 (L2/L3) ready state for the electronic device.

4. The system of claim 1, wherein a runtime element is used to enable the PHY to be power gated.

5. The system of claim 1, wherein a receiver termination remains enabled and a transmitter common mode is turned off as the PHY is power gated.

6. The system of claim 1, wherein power is to be removed from the electronic device such that the electronic device resides in a low power device power state and a root port remains in a system working state.

7. A method comprising:

identifying a power management event (PME) timeout in a computing system;

directing a receiver in a physical layer (PHY) to turn off;

transitioning from a powered-on link state to a recovery state; and

resuming a detection state of a link in the computing system, wherein the detection state is associated with a predetermined timeout associated with failing to receive a sequence from the electronic device, and the detection state is resumed before clearing a runtime-entry configuration bit for the electronic device.

8. The method of claim 7, wherein incoming data is cut off from the electronic device in response to the PHY being turned off.

9. The method of claim 7, wherein the detection state is resumed before indicating a layer 2/layer 3 (L2/L3) ready state for the electronic device.

10. The method of claim 7, wherein a runtime element is used to enable the PHY to be power gated.

11. The method of claim 7, wherein a receiver termination remains enabled and a transmitter common mode is turned off as the PHY is power gated.

12. The method of claim 7, wherein power is to be removed from the electronic device such that the electronic device resides in a low power device power state and a root port remains in a system working state.