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System and method for power management

  • US 10,248,183 B2
  • Filed: 12/06/2016
  • Issued: 04/02/2019
  • Est. Priority Date: 01/04/2013
  • Status: Active Grant
First Claim
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1. A system, comprising:

  • a processor; and

    a memory to store instructions executable by the processor to perform operations comprising;

    identifying a power management event (PME) timeout;

    directing a receiver in a physical layer (PHY) to turn off;

    transitioning from a powered-on link state to a recovery state; and

    resuming a detection state associated with a predetermined timeout associated with failing to receive a sequence from the electronic device, wherein the detection state is resumed before clearing a runtime-entry configuration bit for the electronic device.

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