Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks

• US 10,248,317 B2
• Filed: 06/08/2017
• Issued: 04/02/2019
• Est. Priority Date: 12/28/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Yano, Hirokuni, Kanno, Shinichi, Hida, Toshikatsu, Matsuzaki, Hidenori, Kitsunai, Kazuya, Asano, Shigehiro
• Primary Examiner(s): Verbrugge, Kevin
• Application Number:
  US15/617,220
• Publication Number:
  US 20170269843A1
• Time in Patent Office: 663 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits

Abstract

A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Claims

1. A semiconductor storage device comprising:

a nonvolatile memory having a plurality of blocks, each of the plurality of blocks being a unit of data erasing; and

a controller configured to;

allocate a first set of the plurality of blocks as a first memory area, the first set of the plurality of blocks including SLC (Single Level Cell) blocks;

allocate a second set of the plurality of blocks as a second memory area, the second set of the plurality of blocks including SLC blocks and MLC (Multi Level Cell) blocks;

store data received from an external host apparatus in the SLC block included in the first memory area by a first management unit, the first management unit being less than the unit of data erasing;

copy valid data stored in the SLC blocks to one of the MLC blocks;

release at least one of the SLC blocks in which no valid data is stored from the second memory area, after copying the valid data stored in the SLC blocks, and

wherein the SLC blocks include pseudo SLC blocks.

2. The semiconductor storage device according to claim 1, wherein the controller is configured to allocate the second set of the plurality of blocks to the second memory area when a number of valid data stored in at least one of the SLC blocks included in the first memory area is a first threshold or more.

3. The semiconductor storage device according to claim 2, wherein the controller is configured to copy valid data stored in at least one of the SLC blocks included in the first memory area to one of the MLC blocks when the number of valid data stored in the at least one of the SLC blocks included in the first memory area is less than the first threshold.

4. The semiconductor storage device according to claim 1, wherein the controller is configured to copy valid data stored in the SLC blocks to one of the MLC blocks, within the second memory area, when a first condition is satisfied, the first condition being satisfied when a number of the SLC and MLC blocks allocated to the second memory are exceeds a second threshold.

5. The semiconductor storage device according to claim 1, wherein a programming time for an SLC block is shorter than that for an MLC block.

6. The semiconductor storage device according to claim 1, wherein a capacity of an SLC block is smaller than that of an MLC block.

7. The semiconductor storage device according to claim 6, wherein the controller is configured to invalidate first data, the first data having the same logical address as data newly stored to the first memory area, stored in the first or second memory area.

8. The semiconductor storage device according to claim 7, wherein the controller is configured to manage the SLC blocks allocated to the first memory area with FIFO (First In First Out) data structure sorted by an allocation order.

9. The semiconductor storage device according to claim 8, wherein the controller is configured to, when storing data to the first memory area, allocate a new SLC block to the first memory area at an input side of the FIFO data structure.

10. The semiconductor storage device according to claim 9, wherein the controller is configured to allocate an SLC block having an oldest allocation order at an output side of the FIFO data structure to the second memory area.

11. The semiconductor storage device according to claim 1, wherein a number of blocks allocatable to the first memory area has an upper limit.

12. The semiconductor storage device according to claim 11, wherein the controller is configured to allocate at least one of the SLC blocks to the second memory area when a number of the SLC blocks allocated to the first memory area exceeds the upper limit.

13. The semiconductor storage device according to claim 1, wherein the nonvolatile memory is a NAND type flash memory.

14. The semiconductor storage device according to claim 1, wherein the nonvolatile memory includes a plurality of memory chips.

15. The semiconductor storage device according to claim 1 further comprising a first memory configured to store the data by a first unit or less, the first unit being an access unit from the external host apparatus, the first memory being a DRAM (Dynamic Random Access Memory).

16. A method of controlling a semiconductor storage device, the semiconductor storage device including a nonvolatile memory, the method comprising:

receiving data from an external host apparatus;

allocating a first set of the plurality of blocks as a first memory area, the first set of the plurality of blocks including SLC (Single Level Cell) blocks;

allocating a second set of the plurality of blocks as a second memory area, the second set of the plurality of blocks including SLC blocks and MLC (Multi Level Cell) blocks;

storing the data in the SLC block included in the first memory area by a first management unit, the first management unit being less than the unit of data erasing;

copying valid data stored in the SLC blocks to one of the MLC blocks;

releasing at least one of the SLC blocks in which no valid data is stored from the second memory area, after copying the valid data stored in the SLC blocks, and

wherein the SLC blocks include pseudo SLC blocks.

17. The method according to claim 16, wherein the allocating the second set of the plurality of blocks is executed when a number of valid data stored in at least one of the SLC blocks included in the first memory area is a first threshold or more.

18. The method according to claim 17, wherein the copying is executed when the number of valid data stored in the at least one of the SLC blocks included in the first memory area is less than the first threshold.

19. The method according to claim 16, wherein the copying includes copying valid data stored in the SLC blocks to one of the MLC blocks, within the second memory area, when a condition is satisfied, the condition being satisfied when a number of the SLC and MLC blocks allocated to the second memory area exceeds a second threshold.