Direct data move between DRAM and storage on a memory module
First Claim
1. A computer system, comprising:
- a system memory bus providing a memory channel, the memory channel comprising a control/address (C/A) bus and a data bus;
a processor coupled to the system memory bus;
a memory module including a circuit board having electrical contacts coupled to the system memory bus, a volatile memory unit mounted on the circuit board, a non-volatile memory unit mounted on the circuit board and a control circuit mounted on the circuit board, the volatile memory unit comprising DRAM devices, and the non-volatile memory unit comprising flash memory;
input/output devices coupled to the system bus;
wherein the processor is configured to execute an operating system (OS) and an application program and to present a memory address space to the application program, the memory address space including a memory mapped input/output (MMIO) space mapped to the I/O devices, a pseudo MMIO (PMMIO) space mapped to the non-volatile memory unit, and a DRAM space mapped to the volatile memory unit, the PMMIO space including a system main memory local storage (MMLS) area and a memory channel storage (MCS) area, wherein the DRAM space is partitioned into memory pages, and the MCS area is partitioned into storage blocks;
wherein the operating system is configured to request direct data transfer for one or more storage blocks in the MCS area between the volatile memory unit and the non-volatile memory unit to store or retrieve files associated with the application program by causing a direct data transfer command to be sent to the memory module via the memory channel, the direct data transfer command including an address in the DRAM space and an address in the MCS space; and
wherein the control circuit is configured to receive the direct data transfer command from the memory channel, and to move the data for the one or more storage blocks between the volatile memory unit and the non-volatile memory unit without any of the data for the one or more storage blocks going through the memory channel;
wherein the processor is further configured to respond to a request from the application program to access a memory page not loaded in the volatile memory by causing a page-in command to be transmitted via the data bus to the memory module, the page-in command including information for the memory page and one or more address locations in the MMLS space where the requested data is to be retrieved;
wherein the control circuit is configured to receive the page-in command from the memory channel, to read the data for the memory page from the MMLS space without any of the data for the memory page going through the memory channel;
wherein the processor is further configured to cause a dummy write command to be transmitted to the volatile memory unit, the dummy write command including an address associated with the memory page;
wherein the volatile memory unit further comprises a registered control device (RCD) that is configured to receive the dummy write command from the memory channel, and wherein the DRAM devices are configured to receive the data for the memory page from the control circuit in response to control/address signals from the RCD, the control/address signals being derived from the dummy write command.
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Accused Products
Abstract
A computer system comprises a processor, a memory module and input/output devices. The memory module includes a circuit board, a volatile memory unit mounted on the circuit board, a non-volatile memory unit mounted on the circuit board and a control circuit mounted on the circuit board. The volatile memory unit comprises DRAM devices, and the non-volatile memory unit comprises flash memory. The processor is configured to execute an operating system (OS) and an application program and to present a memory address space to the application program. The memory address space including a memory mapped input/output (MMIO) space mapped to the I/O devices, a pseudo MMIO (PMMIO) space mapped to the non-volatile memory unit, and a DRAM space mapped to the volatile memory unit, the PMMIO space including a system main memory local storage (MMLS) area and a memory channel storage area, wherein the DRAM space is partitioned into memory pages, and the MCS space is partitioned into storage blocks.
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Citations
18 Claims
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1. A computer system, comprising:
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a system memory bus providing a memory channel, the memory channel comprising a control/address (C/A) bus and a data bus; a processor coupled to the system memory bus; a memory module including a circuit board having electrical contacts coupled to the system memory bus, a volatile memory unit mounted on the circuit board, a non-volatile memory unit mounted on the circuit board and a control circuit mounted on the circuit board, the volatile memory unit comprising DRAM devices, and the non-volatile memory unit comprising flash memory; input/output devices coupled to the system bus; wherein the processor is configured to execute an operating system (OS) and an application program and to present a memory address space to the application program, the memory address space including a memory mapped input/output (MMIO) space mapped to the I/O devices, a pseudo MMIO (PMMIO) space mapped to the non-volatile memory unit, and a DRAM space mapped to the volatile memory unit, the PMMIO space including a system main memory local storage (MMLS) area and a memory channel storage (MCS) area, wherein the DRAM space is partitioned into memory pages, and the MCS area is partitioned into storage blocks; wherein the operating system is configured to request direct data transfer for one or more storage blocks in the MCS area between the volatile memory unit and the non-volatile memory unit to store or retrieve files associated with the application program by causing a direct data transfer command to be sent to the memory module via the memory channel, the direct data transfer command including an address in the DRAM space and an address in the MCS space; and wherein the control circuit is configured to receive the direct data transfer command from the memory channel, and to move the data for the one or more storage blocks between the volatile memory unit and the non-volatile memory unit without any of the data for the one or more storage blocks going through the memory channel; wherein the processor is further configured to respond to a request from the application program to access a memory page not loaded in the volatile memory by causing a page-in command to be transmitted via the data bus to the memory module, the page-in command including information for the memory page and one or more address locations in the MMLS space where the requested data is to be retrieved; wherein the control circuit is configured to receive the page-in command from the memory channel, to read the data for the memory page from the MMLS space without any of the data for the memory page going through the memory channel; wherein the processor is further configured to cause a dummy write command to be transmitted to the volatile memory unit, the dummy write command including an address associated with the memory page; wherein the volatile memory unit further comprises a registered control device (RCD) that is configured to receive the dummy write command from the memory channel, and wherein the DRAM devices are configured to receive the data for the memory page from the control circuit in response to control/address signals from the RCD, the control/address signals being derived from the dummy write command. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computer system, comprising:
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a system memory bus providing a memory channel, the memory channel comprising a control/address (C/A) bus and a data bus; a memory controller coupled to the system memory bus; a processor coupled to the memory controller; a memory module coupled to the memory controller via the system memory bus, the memory module comprising; a volatile memory unit coupled to the memory channel, the volatile memory unit including a registered control device (RCD) configured to receive input C/A signals from the C/A bus and memory devices configured to perform memory operations in response to output C/A signals from the RCD that are derived from the input C/A signals; a non-volatile (NV) memory unit; and a module control device coupled to the volatile memory unit, the non-volatile memory unit, and the memory channel; wherein the processor is configured to execute an operating system (OS) including a memory module driver configured to cause the memory controller to issue an NV access request to the memory module via the memory channel to transfer first data from the non-volatile memory unit to the volatile memory unit, and to issue a series of dummy write memory commands via the C/A bus after issuing the NV access request, the series of dummy write memory commands including memory addresses related to the NV access operation; wherein the module control device is configured to perform an NV access operation in response to the NV access request, the NV access operation including reading the first data from the non-volatile memory unit in response to the NV access request, and providing a respective portion of the first data to the volatile memory unit in response to a respective dummy write memory command of the series of dummy write memory commands, the respective dummy write memory command being received by both the module control device and the RCD via the C/A bus; wherein the volatile memory unit is configured to receive the respective portion of the first data in response to the respective dummy write memory command. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification