Data storage system with hardware-based message routing

• US 10,248,357 B2
• Filed: 07/06/2017
• Issued: 04/02/2019
• Est. Priority Date: 07/06/2017
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Spencer, Thomas V.
• Primary Examiner(s): Phan, Raymond N
• Application Number:
  US15/642,404
• Publication Number:
  US 20190012113A1
• Time in Patent Office: 635 Days
• Field of Search: 710 52- 57, 710310
• CPC Class Codes: G06F 11/07 Responding to the occurrence of a fault, e.g. fault tolerance
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data storage system may have a first data storage device and a second data storage device connected with a host via a network. The network can consist of a network controller having a message module that generates a buffer progression plan and then assigns a first system message to a first buffer and first computing unit of the first data storage device and assigns a second system message to a second buffer and second computing unit of the second data storage device. The respective first and second computing units may then service the first and second system messages.

Claims

1. A method comprising:

activating a data storage system connecting first and second data storage devices with a host via a network, the network comprising a network controller having a message module;

generating a buffer progression plan with the message module;

assigning a first system message to a first buffer and first computing unit of the first data storage device;

assigning a second system message to a second buffer and second computing unit of the second data storage device;

servicing the first and second system messages with the respective first and second computing units; and

activating firmware with the message module in response to a failure in servicing the first or second system messages.

2. The method of claim 1, wherein the first and second system messages are services concurrently.

3. The method of claim 1, wherein the first and second system messages are services consecutively.

4. The method of claim 1, wherein the first and second system messages are each generated by the message module.

5. The method of claim 1, wherein the buffer progression plan rotates between different buffers at predetermined intervals.

6. The method of claim 1, wherein each buffer is purged after servicing the respective system messages.

7. The method of claim 1, wherein the message module logs the assigned combination of buffer and computing unit.

8. The method of claim 5, wherein each buffer of the buffer progression plan corresponds with a different computing unit.

9. A method comprising:

activating a data storage system connecting first and second data storage devices with a host via a network, the network comprising a network controller having a message module physically resident on-chip in the network controller;

generating a buffer progression plan with the message module;

assigning a first system message to a first buffer and first computing unit of the first data storage device;

assigning a second system message to a second buffer and second computing unit of the second data storage device;

servicing the first and second system messages with the respective first and second computing units; and

assigning a third system message to an off-chip buffer with the message module.

10. The method of claim 9, wherein the message module activates firmware in response to a failure in servicing the first system message.

11. The method of claim 9, wherein the message module executes a message division plan that creates sub-messages distributed to multiple different buffers of the data storage system.

12. The method of claim 9, wherein the message module alters the buffer progression plan in response to detected system performance being below a predetermined threshold.

13. The method of claim 9, wherein the off-chip buffer comprises a non-volatile memory.

14. The method of claim 13, wherein a computing unit of the network controller services the third system message.

15. An apparatus comprising a data storage system connecting first and second data storage devices with a host via a network, the network comprising a network controller having a message module physically resident on-chip in the network controller, the message module configured to generate a buffer progression plan with the message module and execute the buffer progression plan by assigning a first system message to a first buffer and first computing unit of the first data storage device and assigning a second system message to a second buffer and second computing unit of the second data storage device, and assigning a third system message to an off-chip buffer, the first and second system messages respectively serviced with the first and second computing units.

16. The apparatus of claim 15, wherein the network controller comprises a third buffer present on-chip.

17. The apparatus of claim 15, wherein the first and second data storage devices are physically separated.

18. The apparatus of claim 15, wherein each buffer is a volatile type memory.

19. The apparatus of claim 15, wherein the network controller comprises a programmable controller present on-chip.

20. The apparatus of claim 15, wherein the non-volatile memory comprises flash memory.