Arithmetic processing device and control method for arithmetic processing device

• US 10,248,384 B2
• Filed: 06/09/2017
• Issued: 04/02/2019
• Est. Priority Date: 08/03/2016
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Komagata, Makoto, Maruyama, Takumi, Yamamura, Shuji, Nakagawa, Masato, Kuramoto, Masahiro
• Primary Examiner(s): Ngo, Chuong D
• Application Number:
  US15/618,444
• Publication Number:
  US 20180039480A1
• Time in Patent Office: 662 Days
• CPC Class Codes: G06F 17/153 Multidimensional correlation or convolution
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/46 Multiprogramming arrangements
• CPC Class Codes: G06N 20/00 Machine learning
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology

Abstract

A plurality of floating-point registers store data therein. A processing execution unit executes arithmetic processing by using data stored in the floating-point registers. A first switch and a second switch select a route connecting the processing execution unit and the floating-point registers. A switch control unit controls the first switch and the second switch so as to switch a route to be selected, based on a switching instruction from the processing execution unit.

Claims

1. An arithmetic processing device comprising:

a storage unit that has a plurality of registers;

a processing execution unit that performs a convolution operation by executing a predetermined number of multiply add operations in parallel by one command, by using an image data stored in a plurality of first registers of the storage unit and a filter data stored in a plurality of second registers of the storage unit, when the processing unit acquires a switching completion notice;

a route selection unit that selects a route connecting the processing execution unit and the first and the second registers of the storage units; and

a switching control unit that controls the route selection unit so as to switch the route to be selected, based on a switching instruction from the processing execution unit, and issues the switching completion notice to the processing execution unit.

2. The arithmetic processing device according to claim 1, wherein

the processing execution unit notifies the switching control unit of a switching instruction including information for selecting a switching pattern of the route selection unit, and

the switching control unit includes a plurality of switching patterns in advance, selects the switching pattern according to the switching instruction, and controls the route selection unit according to the selected switching pattern.

3. The arithmetic processing device according to claim 1, wherein

the processing execution unit acquires a command to execute the predetermined number of operations in parallel by one command, notifies the switching instruction according to each of the commands, and retrieves the data from the storage units to perform each of the predetermined number of operations, and

the switching control unit switches the route to be selected by the route selection unit according to each of the predetermined number of operations performed by the processing execution unit.

4. The arithmetic processing device according to claim 1, wherein

the switching control unit controls the route selection unit so as to switch the route to be selected, at a time of reading the data or writing the data by the processing execution unit, and

the processing execution unit executes reading and writing of the data with respect to the storage units via the route selection unit in which the route to be selected has been switched by the switching control unit.

5. A control method for an arithmetic processing device including a storage unit that has a plurality of registers, an processing execution unit, and a route selection unit, the control method comprising:

storing an image data in a plurality of first registers and a filter data in a plurality of second registers of the plurality of registers;

switching the route selection unit so as to switch route connecting the processing execution unit and the first and the second registers of the storage unit to provide the image data and the filter data to the processing execution unit;

issuing a switching completion notice to the processing execution unit; and

causing the processing execution unit to retrieve the filter data and the image data stored in the first and the second registers via the route selected by switching the route selection unit and perform convolution operation to execute a predetermined number of multiply add operations in parallel by one command.