Resource sharing workflows within executable graphical models
First Claim
1. A method comprising:
- storing, in a memory, a first intermediate representation of at least a portion of an executable source model including a plurality of model blocks arranged on data paths;
automatically revising, by a processor coupled to the memory, the first intermediate representation to produce a second intermediate representation of the at least a portion of the executable source model, the second intermediate representation optimized for a hardware implementation of the at least a portion of the executable source model, the automatically revising resulting in one or more delays being introduced into the second intermediate representation;
automatically modifying, by the processor, the second intermediate representation to correct for the one or more delays introduced into the second intermediate representation, the automatically modifying including;
identifying a join point in the second intermediate representation where two of the data paths merge;
computing sums of delays for the two data paths at the join point;
comparing the sums of delays for the two data paths; and
when the sums of delays are unequal, inserting a first delay element into one of the two data paths, the first delay element configured such that the sums of delays are equal, the automatically modifying producing a third intermediate representation of the at least a portion of the executable source model;
generating from the third intermediate representation a hardware description language (HDL) description of the at least a portion of the executable source model; and
configured one or more target hardware elements based on the HDL description.
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Abstract
A system and method optimizes hardware description generated from a graphical program or model automatically. The system may include a streaming optimizer, a resource sharing optimizer and a delay balancing engine. The streaming optimizer transforms one or more vector data paths in the source model to scalar data paths or to a smaller-sized vector data paths. The resource sharing optimizer may replace multiple blocks of the source model that are functionally equivalent with a single shared block. The streaming and resource sharing optimizers may also configure portions of the modified model to execute at a faster rate. The delay balancing engine may examine the modified model to determine whether any delays or latencies have been introduced. If so, the delay balancing engine may insert one or more blocks into the modified model to correct for any data path misalignment caused by the introduction of the delays or latencies. A validation model, a report, or hardware description code that utilizes fewer hardware resources may be generated from the modified model.
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Citations
23 Claims
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1. A method comprising:
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storing, in a memory, a first intermediate representation of at least a portion of an executable source model including a plurality of model blocks arranged on data paths; automatically revising, by a processor coupled to the memory, the first intermediate representation to produce a second intermediate representation of the at least a portion of the executable source model, the second intermediate representation optimized for a hardware implementation of the at least a portion of the executable source model, the automatically revising resulting in one or more delays being introduced into the second intermediate representation; automatically modifying, by the processor, the second intermediate representation to correct for the one or more delays introduced into the second intermediate representation, the automatically modifying including; identifying a join point in the second intermediate representation where two of the data paths merge; computing sums of delays for the two data paths at the join point; comparing the sums of delays for the two data paths; and when the sums of delays are unequal, inserting a first delay element into one of the two data paths, the first delay element configured such that the sums of delays are equal, the automatically modifying producing a third intermediate representation of the at least a portion of the executable source model; generating from the third intermediate representation a hardware description language (HDL) description of the at least a portion of the executable source model; and configured one or more target hardware elements based on the HDL description. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. One or more non-transitory, computer-readable media including instructions executable by a processor, the instructions comprising instructions for:
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storing, in a memory, a first in-memory representation of at least a portion of an executable source model including a plurality of model blocks arranged on data paths; automatically revising, by a processor coupled to the memory, the first in-memory representation to produce a second in-memory representation of the at least a portion of the executable source model, the second in-memory representation optimized for a hardware implementation of the at least a portion of the executable source model, the automatically revising resulting in one or more delays being introduced into the second in-memory representation; automatically modifying, by the processor, the second in-memory representation to correct for the one or more delays introduced into the second intermediate representation, the automatically modifying including; identifying a join point in the second in-memory representation where two of the data paths merge; computing sums of delays for the two data paths at the join point; comparing the sums of delays for the two data paths; and when the sums of delays are unequal, inserting a first delay element into one of the two data paths, the first delay element configured such that the sums of delays are equal, the automatically modifying producing a third in-memory representation of the at least a portion of the executable source model; and generating from the third in-memory representation a hardware description language (HDL) description of the at least a portion of the executable source model; and configured one or more target hardware elements based on the HDL description. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. An apparatus comprising:
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a memory storing a first intermediate representation of at least a portion of an executable source model including a plurality of model blocks arranged on data paths; and a processor coupled to the memory, the processor configured to; automatically revise the first intermediate representation to produce a second intermediate representation of the at least a portion of the executable source model, the second intermediate representation optimized for a hardware implementation of the at least a portion of the executable source model, the automatically revising resulting in one or more delays being introduced into the second intermediate representation; automatically modify the second intermediate representation to correct for the one or more delays introduced into the second intermediate representation, the automatically modifying including; identify a join point in the second intermediate representation where two of the data paths merge; compute sums of delays for the two data paths at the join point; compare the sums of delays for the two data paths; and when the sums of delays are unequal, insert a first delay element into one of the two data paths, the first delay element configured such that the sums of delays are equal, the automatically modifying producing a third intermediate representation of the at least a portion of the executable source model; and generate from the third intermediate representation code for the at least a portion of the executable source model; and configured one or more target hardware elements based on the code. - View Dependent Claims (20, 21, 22, 23)
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Specification