Resource sharing workflows within executable graphical models

• US 10,248,390 B1
• Filed: 01/12/2016
• Issued: 04/02/2019
• Est. Priority Date: 12/09/2009
• Status: Active Grant

• Current Assignee: The MathWorks, Inc.
• Original Assignee: The MathWorks, Inc.
• Inventors: Venkataramani, Girish, Kintali, Kiran
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US14/993,773
• Time in Patent Office: 1,176 Days
• Field of Search: 716100, 716104, 716105, 716108, 716111, 716116, 716122, 716124, 716125, 716131, 716132, 703 16
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/31 Design entry, e.g. editors specifically adapted for circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06F 8/34 Graphical or visual programming
• CPC Class Codes: G06F 8/35 model driven

Abstract

A system and method optimizes hardware description generated from a graphical program or model automatically. The system may include a streaming optimizer, a resource sharing optimizer and a delay balancing engine. The streaming optimizer transforms one or more vector data paths in the source model to scalar data paths or to a smaller-sized vector data paths. The resource sharing optimizer may replace multiple blocks of the source model that are functionally equivalent with a single shared block. The streaming and resource sharing optimizers may also configure portions of the modified model to execute at a faster rate. The delay balancing engine may examine the modified model to determine whether any delays or latencies have been introduced. If so, the delay balancing engine may insert one or more blocks into the modified model to correct for any data path misalignment caused by the introduction of the delays or latencies. A validation model, a report, or hardware description code that utilizes fewer hardware resources may be generated from the modified model.

Claims

1. A method comprising:

storing, in a memory, a first intermediate representation of at least a portion of an executable source model including a plurality of model blocks arranged on data paths;

automatically revising, by a processor coupled to the memory, the first intermediate representation to produce a second intermediate representation of the at least a portion of the executable source model, the second intermediate representation optimized for a hardware implementation of the at least a portion of the executable source model, the automatically revising resulting in one or more delays being introduced into the second intermediate representation;

automatically modifying, by the processor, the second intermediate representation to correct for the one or more delays introduced into the second intermediate representation, the automatically modifying including;

identifying a join point in the second intermediate representation where two of the data paths merge;

computing sums of delays for the two data paths at the join point;

comparing the sums of delays for the two data paths; and

when the sums of delays are unequal, inserting a first delay element into one of the two data paths, the first delay element configured such that the sums of delays are equal, the automatically modifying producing a third intermediate representation of the at least a portion of the executable source model;

generating from the third intermediate representation a hardware description language (HDL) description of the at least a portion of the executable source model; and

configured one or more target hardware elements based on the HDL description.

2. The method of claim 1 wherein the two data paths have different rates, the automatically modifying further including:

normalizing the different rates of the two data paths before the computing.

3. The method of claim 2 wherein the rates of the two data paths are based on at least one of sample rates, time steps, or event steps.

4. The method of claim 1 further comprising:

identifying a rate transition boundary in the second intermediate representation; and

inserting a second delay element at the rate transition boundary.

5. The method of claim 4 wherein the rate transition boundary occurs at an upsample element or a downsample element of the at least a portion of the executable source model.

6. The method of claim 4 further comprising:

configuring the second delay element to provide a delay given by;

K−

(N % K), where

N is a number of new delays introduced at the rate transition boundary,

% is a modulo operation, and

K is a rate transition factor.

7. The method of claim 1 wherein the executable source model is a textual model, a graphical model, or a combination textual-graphical model.

8. The method of claim 1 wherein the automatically revising includes at least one of a resource sharing optimization, a streaming optimization, and a pipelining optimization to the first intermediate representation.

9. The method of claim 1 wherein the at least a portion of the executable source model includes a given data path of the data paths, the given data path including a first vector width, and the automatically revising includes:

converting at least a portion of the given data path from the first vector width to a scalar or a second vector width, where the second vector width is smaller than the first vector width.

10. One or more non-transitory, computer-readable media including instructions executable by a processor, the instructions comprising instructions for:

storing, in a memory, a first in-memory representation of at least a portion of an executable source model including a plurality of model blocks arranged on data paths;

automatically revising, by a processor coupled to the memory, the first in-memory representation to produce a second in-memory representation of the at least a portion of the executable source model, the second in-memory representation optimized for a hardware implementation of the at least a portion of the executable source model, the automatically revising resulting in one or more delays being introduced into the second in-memory representation;

automatically modifying, by the processor, the second in-memory representation to correct for the one or more delays introduced into the second intermediate representation, the automatically modifying including;

identifying a join point in the second in-memory representation where two of the data paths merge;

computing sums of delays for the two data paths at the join point;

comparing the sums of delays for the two data paths; and

when the sums of delays are unequal, inserting a first delay element into one of the two data paths, the first delay element configured such that the sums of delays are equal, the automatically modifying producing a third in-memory representation of the at least a portion of the executable source model; and

generating from the third in-memory representation a hardware description language (HDL) description of the at least a portion of the executable source model; and

configured one or more target hardware elements based on the HDL description.

11. The one or more non-transitory, computer-readable media of claim 10 wherein the two data paths have different rates, the automatically modifying further including:

normalizing the different rates of the two data paths before the computing.

12. The one or more non-transitory, computer-readable media of claim 11 wherein the rates of the two data paths are based on at least one of sample rates, time steps, or event steps.

13. The one or more non-transitory, computer-readable media of claim 10 further comprising instructions for:

identifying a rate transition boundary in the second in-memory representation; and

inserting a second delay element at the rate transition boundary.

14. The one or more non-transitory, computer-readable media of claim 13 wherein the rate transition boundary occurs at an upsample element or a downsample element of the at least a portion of the executable source model.

15. The one or more non-transitory, computer-readable media of claim 13 further comprising instructions for:

configuring the second delay element to provide a delay given by;

K−

(N % K), where

N is a number of new delays introduced at the rate transition boundary,

% is a modulo operation, and

K is a rate transition factor.

16. The one or more non-transitory, computer-readable media of claim 10 wherein the executable source model is a textual model, a graphical model, or a combination textual-graphical model.

17. The one or more non-transitory, computer-readable media of claim 10 wherein the automatically revising includes at least one of a resource sharing optimization, a streaming optimization, and a pipelining optimization to the first in-memory representation.

18. The one or more non-transitory, computer-readable media of claim 10 wherein the at least a portion of the executable source model includes a given data path of the data paths, the given data path including a first vector width, and the instructions for automatically revising include instructions for:

converting at least a portion of the given data path from the first vector width to a scalar or a second vector width, where the second vector width is smaller than the first vector width.

19. An apparatus comprising:

a memory storing a first intermediate representation of at least a portion of an executable source model including a plurality of model blocks arranged on data paths; and

a processor coupled to the memory, the processor configured to;

automatically revise the first intermediate representation to produce a second intermediate representation of the at least a portion of the executable source model, the second intermediate representation optimized for a hardware implementation of the at least a portion of the executable source model, the automatically revising resulting in one or more delays being introduced into the second intermediate representation;

automatically modify the second intermediate representation to correct for the one or more delays introduced into the second intermediate representation, the automatically modifying including;

identify a join point in the second intermediate representation where two of the data paths merge;

compute sums of delays for the two data paths at the join point;

compare the sums of delays for the two data paths; and

when the sums of delays are unequal, insert a first delay element into one of the two data paths, the first delay element configured such that the sums of delays are equal, the automatically modifying producing a third intermediate representation of the at least a portion of the executable source model; and

generate from the third intermediate representation code for the at least a portion of the executable source model; and

configured one or more target hardware elements based on the code.

20. The apparatus of claim 19 wherein the two data paths have different rates, the processor further configured to:

normalize the different rates of the two data paths before the computing.

21. The apparatus of claim 20 wherein the rates of the two data paths are based on at least one of sample rates, time steps, or event steps.

22. The apparatus of claim 19 wherein the processor is further configured to:

identify a rate transition boundary in the second intermediate representation; and

insert a second delay element at the rate transition boundary.

23. The apparatus of claim 19 wherein the automatically revising includes at least one of a resource sharing optimization, a streaming optimization, and a pipelining optimization to the first intermediate representation.