Providing additional memory and cache for the execution of critical tasks by folding processing units of a processor complex

• US 10,248,464 B2
• Filed: 10/24/2016
• Issued: 04/02/2019
• Est. Priority Date: 10/24/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Borlick, Matthew G., Gupta, Lokesh M., Nguyen, Trung N.
• Primary Examiner(s): Schnee, Hal
• Application Number:
  US15/332,660
• Publication Number:
  US 20180113744A1
• Time in Patent Office: 890 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/151 Emulated environment, e.g. virtual machine
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 2212/6042 Allocation of cache space to multiple users or processors
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

A plurality of processing entities of a processor complex is maintained, wherein each processing entity has a local cache and the processor complex has a shared cache and a shared memory. One of the plurality of processing entities is allocated for execution of a critical task. In response to the allocating of one of the plurality of processing entities for the execution of the critical task, other processing entities of the plurality of processing entities are folded. The critical task utilizes the local cache of the other processing entities that are folded, the shared memory, and the shared cache, in addition to the local cache of the processing entity allocated for the execution of the critical task.

Claims

1. A method, comprising:

maintaining a plurality of processing entities of a processor complex, wherein each processing entity has a local cache and the processor complex has a shared cache and a shared memory;

allocating one of the plurality of processing entities for execution of a critical task;

in response to the allocating of one of the plurality of processing entities for the execution of the critical task, folding other processing entities of the plurality of processing entities by stopping processing operations in the other processing entities and releasing the local cache of the other processing entities for use by the processing entity allocated for execution of the critical task, wherein prior to folding the other processing entities, currently scheduled tasks on the other processing entities are temporarily suspended;

utilizing, by the critical task, the local cache of the other processing entities that are folded, the shared memory, additional resources that are freed by folding the other processing entities, and the shared cache, in addition to the local cache of the processing entity allocated for the execution of the critical task;

in response to completion of the critical task in the processing entity that is allocated, performing an unfolding of the other processing entities to make the other processing entities operational; and

in response to performing the unfolding of the other processing entities, resuming any suspended tasks and dispatch queued tasks.

2. The method of claim 1, wherein it is preferable to execute the critical task on a single processing entity in comparison to more than one processing entity.

3. The method of claim 1, wherein the plurality of processing entities comprises a plurality of cores of a chip, wherein the local cache comprises an L1 and an L2 cache, and the shared cache comprises an L3 cache of the chip.

4. The method of claim 1, wherein the plurality of processing entities comprises a plurality of virtual processors implemented via software or firmware.

5. A system, comprising:

a processor;

a computer readable storage medium having program instructions embodied therewith, the program instructions executable by the processor to cause the processor to perform operations, the operations comprising;

maintaining a plurality of processing entities, wherein each processing entity has a local cache;

allocating one of the plurality of processing entities for execution of a critical task;

in response to the allocating of one of the plurality of processing entities for the execution of the critical task, folding other processing entities of the plurality of processing entities by stopping processing operations in the other processing entities and releasing the local cache of the other processing entities for use by the processing entity allocated for execution of the critical task, wherein prior to folding the other processing entities, currently scheduled tasks on the other processing entities are temporarily suspended;

utilizing, by the critical task, the local cache of the other processing entities that are folded, a shared memory, additional resources that are freed by folding the other processing entities, and a shared cache, in addition to the local cache of the processing entity allocated for the execution of the critical task;

in response to completion of the critical task in the processing entity that is allocated, performing an unfolding of the other processing entities to make the other processing entities operational; and

in response to performing the unfolding of the other processing entities, resuming any suspended tasks and dispatch queued tasks.

6. The system of claim 5, wherein it is preferable to execute the critical task on a single processing entity in comparison to more than one processing entity.

7. The system of claim 5, wherein the plurality of processing entities comprises a plurality of cores of a chip, wherein the local cache comprises an L1 and an L2 cache, and the shared cache comprises an L3 cache of the chip.

8. The system of claim 5, wherein the plurality of processing entities comprises a plurality of virtual processors implemented via software or firmware.

9. A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable to perform operations, the operations comprising:

maintaining a plurality of processing entities of a processor complex, wherein each processing entity has a local cache and the processor complex has a shared cache and a shared memory;

allocating one of the plurality of processing entities for execution of a critical task;

in response to the allocating of one of the plurality of processing entities for the execution of the critical task, folding other processing entities of the plurality of processing entities by stopping processing operations in the other processing entities and releasing the local cache of the other processing entities for use by the processing entity allocated for execution of the critical task, wherein prior to folding the other processing entities, currently scheduled tasks on the other processing entities are temporarily suspended;

utilizing, by the critical task, the local cache of the other processing entities that are folded, a shared memory, additional resources that are freed by folding the other processing entities, and the shared cache, in addition to the local cache of the processing entity allocated for the execution of the critical task;

in response to completion of the critical task in the processing entity that is allocated, performing an unfolding of the other processing entities to make the other processing entities operational; and

in response to performing the unfolding of the other processing entities, resuming any suspended tasks and dispatch queued tasks.

10. The computer program product of claim 9, wherein it is preferable to execute the critical task on a single processing entity in comparison to more than one processing entity.

11. The computer program product of claim 9, wherein the plurality of processing entities comprises a plurality of cores of a chip, wherein the local cache comprises an L1 and an L2 cache, and the shared cache comprises an L3 cache of the chip.

12. The computer program product of claim 9, wherein the plurality of processing entities comprises a plurality of virtual processors implemented via software or firmware.

13. A storage system, comprising:

a first server; and

a second server coupled to the first server, wherein the storage system is configurable to perform operations, the operations comprising;

maintaining a plurality of processing entities, wherein each processing entity has a local cache;

allocating one of the plurality of processing entities for execution of a critical task;

in response to the allocating of one of the plurality of processing entities for the execution of the critical task, folding other processing entities of the plurality of processing entities by stopping processing operations in the other processing entities and releasing the local cache of the other processing entities for use by the processing entity allocated for execution of the critical task, wherein prior to folding the other processing entities, currently scheduled tasks on the other processing entities are temporarily suspended;

utilizing, by the critical task, the local cache of the other processing entities that are folded, a shared memory, additional resources that are freed by folding the other processing entities, and a shared cache, in addition to the local cache of the processing entity allocated for the execution of the critical task;

in response to completion of the critical task in the processing entity that is allocated, performing an unfolding of the other processing entities to make the other processing entities operational; and

in response to performing the unfolding of the other processing entities, resuming any suspended tasks and dispatch queued tasks.

14. The storage system of claim 13, wherein it is preferable to execute the critical task on a single processing entity in comparison to more than one processing entity.

15. The storage system of claim 13 wherein the plurality of processing entities comprises a plurality of cores of a chip, wherein the local cache comprises an L1 and an L2 cache, and the shared cache comprises an L3 cache of the chip.

16. The storage system of claim 13, wherein the plurality of processing entities comprises a plurality of virtual processors implemented via software or firmware.

17. A server computational device of a dual-server storage system, the server computational device comprising:

a processor; and

a computer readable storage medium having program instructions embodied therewith, the program instructions executable by the processor to cause the processor to perform operations, the operations comprising;

maintaining a plurality of processing entities, wherein each processing entity has a local cache;

allocating one of the plurality of processing entities for execution of a critical task;

in response to the allocating of one of the plurality of processing entities for the execution of the critical task, folding other processing entities of the plurality of processing entities by stopping processing operations in the other processing entities and releasing the local cache of the other processing entities for use by the processing entity allocated for execution of the critical task, wherein prior to folding the other processing entities, currently scheduled tasks on the other processing entities are temporarily suspended;

utilizing, by the critical task, the local cache of the other processing entities that are folded, a shared memory, additional resources that are freed by folding the other processing entities, and a shared cache, in addition to the local cache of the processing entity allocated for the execution of the critical task;

in response to completion of the critical task in the processing entity that is allocated, performing an unfolding of the other processing entities to make the other processing entities operational; and

in response to performing the unfolding of the other processing entities, resuming any suspended tasks and dispatch queued tasks.

18. The server computational device of claim 17, wherein it is preferable to execute the critical task on a single processing entity in comparison to more than one processing entity.

19. The server computational device of claim 17, wherein the plurality of processing entities comprises a plurality of cores of a chip, wherein the local cache comprises an L1 and an L2 cache, and the shared cache comprises an L3 cache of the chip.

20. The server computational device of claim 17, wherein the plurality of processing entities comprises a plurality of virtual processors implemented via software or firmware.