High speed functional test vectors in low power test conditions of a digital integrated circuit

• US 10,248,520 B2
• Filed: 07/05/2016
• Issued: 04/02/2019
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Vahidsafa, Ali
• Primary Examiner(s): Bonzo, Bryce P
• Assistant Examiner(s): Arcos, Jeison C
• Application Number:
  US15/202,308
• Publication Number:
  US 20170091059A1
• Time in Patent Office: 1,001 Days
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers

Abstract

Implementations of the present disclosure involve an apparatus and/or method for conducting an at-speed functional test on a silicon wafer of an integrated circuit. In one embodiment, the method includes utilizing a first clock signal during a first portion of the test and a second clock signal during a second portion. The clock signals are configured such that a first subset of the logic stages of the circuit are tested at-speed by the first portion and a second subset of the logic stages of the circuit are tested at-speed. Further, in one embodiment, the first subset and the second subset comprise all of the logic stages of the circuit design. Through the configuration of the clock signals, the tester may ensure that each stage of the circuit design is tested at-speed such that a more accurate at-speed test result may be obtained in a low current environment.

Claims

1. A method for functional testing of a microelectronic circuit, the method comprising:

loading an initial test value into the microelectronic circuit through one or more inputs to the microelectronic circuit, the microelectronic circuit comprising a plurality of logic stages;

conducting a first portion of a functional test by transmitting a first clock signal to the microelectronic circuit, the first clock signal comprising one or more pulses of a first clock signal and one or more first delay periods, the first clock signal configured to test a first subset of the plurality of logic stages at an operational frequency of the microelectronic circuit;

storing a result of the first portion of the functional test in a memory device;

initializing the microelectronic circuit by reloading the initial value into the microelectronic circuit through the one or more inputs;

conducting a second portion of the functional test by transmitting a second clock signal to the microelectronic circuit, the second clock signal comprising at least one offsetting clock pulse, one or more pulses of a second clock signal and one or more second delay periods, the second clock signal configured to test a second subset of the plurality of logic stages at the operational frequency of the microelectronic circuit, the second subset of the plurality of logic stages different than the first subset, the one or more first delay periods of the first clock signal and the one or more second delay periods of the second clock signal causing a charge for one or more components of the microelectronic circuit to replenish; and

comparing the stored result from the first portion and a result from the second portion to an expected result.

2. The method of claim 1 wherein the one or more clock pulses of the first clock signal have a first frequency and the one or more clock pulses of the second clock signal have a second frequency, wherein the first frequency and the second frequency are equal to the operational frequency of the microelectronic circuit.

3. The method of claim 2 wherein the one or more clock pulses of the first clock signal and the second clock signal both comprise n clock pulses at the operational frequency of the microelectronic circuit.

4. The method of claim 2 wherein the one or more delay periods of the first clock signal and the second clock signal both comprise no clock pulses for a length of time equal to m clock pulses of the operational frequency of the microelectronic circuit.

5. The method of claim 4 wherein the m clock pulses is more than the n clock pulses.

6. The method of claim 1 wherein a combination of the first subset of the plurality of logic states and the second subset of the plurality of logic states include all of the plurality of logic states of the microelectronic circuit.

7. The method of claim 1 wherein the microelectronic circuit is embodied on a silicon wafer and the first portion of the functional test is conducted by a wafer tester, the wafer tester replenishing the charge by providing a current to the silicon wafer.

8. The method of claim 1 further comprising:

obtaining the result of the first portion of the functional test from the memory device, wherein the expected result is a checksum value and comparing the stored result from the first portion to the expected result comprises determining if the checksum value is equal to the stored result from the first portion of the functional test.

9. The method of claim 8 further comprising:

obtaining the result of the second portion of the functional test; and

comparing the result of the second portion to the expected result to determine if the checksum value is equal to the result of the second portion of the functional test.

10. A computer system comprising:

a testing device for conducting testing of circuit designs; and

a microelectronic circuit embodied on a silicon wafer and coupled to the testing device, the microelectronic circuit comprising a plurality of logic stages;

wherein the testing device electrically connects to the microelectronic circuit and is configured to;

load an initial test value into the microelectronic circuit through one or more inputs to the microelectronic circuit;

initiate a first portion of an at-speed test by transmitting a first clock signal to the microelectronic circuit, the first clock signal comprising one or more pulses of a first clock signal and one or more first delay periods, the first clock signal configured to test a first subset of the plurality of logic stages at an operational frequency of the microelectronic circuit;

store a result of the first portion of the at-speed test in a memory device;

initialize the microelectronic circuit by reloading the initial test value into the microelectronic circuit through the one or more inputs;

conduct a second portion of the at-speed test by transmitting a second clock signal to the microelectronic circuit, the second clock signal comprising at least one offsetting clock pulse, one or more pulses of a second clock signal and one or more second delay periods, the second clock signal configured to test a second subset of the plurality of logic stages at the operational frequency of the microelectronic circuit, the second subset of the plurality of logic stages different than the first subset, the one or more first delay periods of the first clock signal and the one or more second delay periods of the second clock signal causing a charge for one or more components of the microelectronic circuit to replenish; and

compare the stored result from the first portion and a result from the second portion to an expected result.

11. The computer system of claim 10 wherein the one or more clock pulses of the first clock signal have a first frequency and the one or more clock pulses of the second clock signal have a second frequency, wherein the first frequency and the second frequency are equal to the operational frequency of the microelectronic circuit.

12. The computer system of claim 11 wherein the one or more clock pulses of the first clock signal and the second clock signal both comprise n clock pulses at the operational frequency of the microelectronic circuit.

13. The computer system of claim 11 wherein the one or more delay periods of the first clock signal and the second clock signal both comprise no clock pulses for a length of time equal to m clock pulses of the operational frequency of the microelectronic circuit.

14. The computer system of claim 13 wherein the m clock pulses is more than the n clock pulses.

15. The computer system of claim 10 wherein a combination of the first subset of the plurality of logic states and the second subset of the plurality of logic states include all of the plurality of logic states of the microelectronic circuit.

16. The computer system of claim 10 wherein the testing device is a wafer tester configured to provide power to the microelectronic circuit during the first portion and the second portion of the at-speed test, the wafer tester replenishing the charge by providing the power to the silicon wafer.

17. The computer system of claim 10 wherein the testing device is further configured to obtain the result of the first portion of the at-speed test from the memory device, wherein the expected result is a checksum value and comparing the stored result from the first portion to the expected result comprises determining if the checksum value is equal to the stored result from the first portion of the at-speed test.

18. The computer system of claim 17 wherein the testing device is further configured to:

obtaining the result of the second portion of the at-speed test; and

comparing the result of the second portion to the expected result to determine if the checksum value is equal to the result of the second portion of the at-speed test.