Efficient cache memory having an expiration timer
First Claim
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1. A method, comprising:
- selectively invalidating data stored in at least one cache line of a cache memory of a processor in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed, the predetermined amount of time being shorter than an average round-trip time for the processor to process a plurality of blocks of data stored sequentially to a ring buffer.
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Abstract
In one embodiment, a method includes selectively invalidating data stored in at least one cache line of a cache memory of a processor in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed. The predetermined amount of time is shorter than an average round-trip time for the processor to process a plurality of blocks of data stored sequentially to a ring buffer. In other embodiments, methods, systems, and computer program products are described for efficient use of cache memory using an expiration timer.
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Citations
18 Claims
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1. A method, comprising:
selectively invalidating data stored in at least one cache line of a cache memory of a processor in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed, the predetermined amount of time being shorter than an average round-trip time for the processor to process a plurality of blocks of data stored sequentially to a ring buffer. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A system, comprising:
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a processing circuit having a cache memory therein; a ring buffer; and logic integrated with the processing circuit, executable by the processing circuit, or integrated with and executable by the processing circuit, the logic being configured to cause the processing circuit to; selectively invalidate data stored in at least one cache line of the cache memory in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed, the predetermined amount of time being shorter than an average round-trip time for the processing circuit to process a plurality of blocks of data stored sequentially to the ring buffer. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the embodied program instructions being executable by a processing circuit to cause the processing circuit to:
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selectively invalidate, by the processing circuit, data stored in at least one cache line of a cache memory in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed, wherein the predetermined amount of time is shorter than an average round-trip time for the processing circuit to process a plurality of blocks of data stored sequentially to a ring buffer, and wherein the processing circuit comprises the cache memory. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification