Microcontroller programmable system on a chip

• US 10,248,604 B2
• Filed: 03/08/2017
• Issued: 04/02/2019
• Est. Priority Date: 10/26/2000
• Status: Expired due to Fees

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren S., Mar, Monte
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US15/453,492
• Publication Number:
  US 20170177536A1
• Time in Patent Office: 755 Days
• Field of Search: None
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/25033 structure, control, syncronization, data, alarm, connect I-O line to interface
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/7817 Specially adapted for signal processing, e.g. Harvard architectures
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H03B 5/32 being a piezoelectric resonator selection of piezoelectric material H10N30/00
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03H 19/004 Switched capacitor networks
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

Claims

1. A configurable analog processing circuit, comprising:

a plurality of analog circuit blocks, each configured to provide at least one analog function;

a programmable interconnect coupled to the analog circuit blocks, the programmable interconnect configurable to interconnect combinations of at least two of the plurality of analog circuit blocks to one another to perform at least another analog function; and

at least one digital block of a plurality of digital blocks that each provides at least one digital function, and wherein the programmable interconnect is further coupled to the plurality of digital blocks and configurable to interconnect combinations of the plurality of digital blocks to one another,

wherein the circuit is formed in an integrated circuit and wherein the programmable interconnect comprises a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the integrated circuit,

wherein the plurality of switches are configured in one or more multiplexer (MUX) circuits, the MUX circuits comprising MUX inputs and MUX outputs coupled to the analog circuit blocks.

2. The configurable analog processing circuit of claim 1, wherein the one or more MUX circuits comprise block MUX circuits coupled to the analog circuits.

3. The configurable analog processing circuit of claim 1, wherein the programmable interconnect is programmable to provide multiple signal paths between same analog circuit blocks.

4. The configurable analog processing circuit of claim 1, wherein the analog circuit blocks are selected from the group of:

analog continuous time amplifiers and switched capacitor type circuits.

5. A method, comprising:

forming a plurality of analog circuit blocks in an integrated circuit;

forming a plurality of digital circuit blocks on the integrated circuit, the plurality of digital blocks to perform at least one digital function; and

forming a programmable interconnect to at least enable combinations of at least two of the plurality of analog circuit blocks to be interconnected to perform combined analog functions of the analog circuit blocks using a plurality of switches coupled between the analog circuit blocks and ports that provide signal connections for the integrated circuit, the programmable interconnect coupled to the plurality of digital blocks to interconnect combinations of the plurality of digital blocks to one another, wherein the plurality of switches are configured in one or more multiplexer (MUX) circuits, the MUX circuits comprising MUX inputs and MUX outputs coupled to at least one of the analog circuit blocks.

6. The method of claim 5, further comprising enabling any of the analog circuit blocks to be connected to at least one port that provides a signal connection point to the integrated circuit using the programmable interconnect.

7. The method of claim 5, further comprising:

providing at least one digital circuit block in the integrated circuit; and

enabling any of the digital circuit blocks to be interconnected to combine digital functions of the digital circuit blocks using the programmable interconnect.

8. The method of claim 5, further comprising enabling at least two analog circuit blocks to be coupled in series using the programmable interconnect.

9. The method of claim 5, further comprising enabling any of the analog circuit blocks to be connected to the at least one digital circuit block using the programmable interconnect.

10. The method of claim 5, further comprising providing an analog signal output path from any of the analog circuit blocks to the at least one port.