Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating

• US 10,249,368 B2
• Filed: 02/10/2018
• Issued: 04/02/2019
• Est. Priority Date: 10/13/2011
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US15/893,623
• Publication Number:
  US 20180182460A1
• Time in Patent Office: 416 Days
• CPC Class Codes: G11C 11/21 using electric elements
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0027 and the nonvolatile element is a ferroelectric element
• CPC Class Codes: G11C 14/0036 and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 14/009 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/00 Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching integrated devices or assemblies of multiple devices H10N79/00
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 : Complex metal oxides, e.g. perovskites, spinels

Abstract

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

Claims

1. A semiconductor memory array comprising:

a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include;

a floating body region;

a non-volatile memory comprising a bipolar resistive change element;

wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on resistivity of said bipolar resistive change element, upon restoration of power to said memory cell;

wherein said array is configured to perform a restore operation on said at least two of said memory cells in parallel.

2. The semiconductor memory array of claim 1, wherein said memory cell functions as volatile memory upon said restoration of power to said memory cell.

3. The semiconductor memory array of claim 1, wherein said floating body region is configured to a predetermined state prior to being charged based on resistivity of said bipolar resistive change element.

4. The semiconductor memory array of claim 1, wherein said bipolar resistive change element is configured to a predetermined resistivity after said floating body region is charged to a level based on resistivity of said bipolar resistive change element.

5. The semiconductor memory array of claim 1, further comprising a first region in electrical contact with said floating body region and a second region spaced apart from said first region and in electrical contact with said floating body region.

6. The semiconductor memory array of claim 1, wherein said bipolar resistive change element comprises a material selected from at least one of:

transition metal oxide materials, ferroelectric materials and ferromagnetic materials.

7. The semiconductor memory array of claim 1, wherein said bipolar resistive change element is electrically connected to said floating body region and a distance between said bipolar resistive change element and said bipolar device, when electrically connected, is in the range from about 90 nm to 1 μ

m.

8. The semiconductor memory array of claim 1, further comprising an addressable line electrically connected to said bipolar resistive change element.

9. The semiconductor memory array of claim 8, wherein said bipolar resistive change element further comprises a conductive material element interconnecting said addressable line and said bipolar resistive change material.

10. The semiconductor memory array of claim 1 comprising a three-dimensional structure comprising a fin structure comprising said floating body region, extending substantially perpendicular to, and above a top surface of a substrate.

11. An integrated circuit comprising:

a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include;

a floating body region;

a non-volatile memory comprising a bipolar resistive change element;

wherein said floating body region is configured to be charged to a level indicative of a state of the memory cell based on resistivity of said bipolar resistive change element, upon restoration of power to said memory cell; and

a circuit configured to perform a restore operation on said at least two of said memory cells in parallel.

12. The integrated circuit of claim 11, wherein said memory cell functions as volatile memory upon said restoration of power to said memory cell.

13. The integrated circuit of claim 11, wherein said floating body region is configured to a predetermined state prior to being charged based on resistivity of said bipolar resistive change element.

14. The integrated circuit of claim 11, wherein said bipolar resistive change element is configured to a predetermined resistivity after said floating body region is charged to a level based on resistivity of said bipolar resistive change element.

15. The integrated circuit of claim 11, further comprising a first region in electrical contact with said floating body region and a second region spaced apart from said first region and in electrical contact with said floating body region.

16. The integrated circuit of claim 11, wherein said bipolar resistive change element comprises a material selected from at least one of:

transition metal oxide materials, ferroelectric materials and ferromagnetic materials.

17. The integrated circuit of claim 11, wherein said bipolar resistive change element is electrically connected to said floating body region and a distance between said bipolar resistive change element and said bipolar device, when electrically connected, is in the range from about 90 nm to 1 μ

m.

18. The integrated circuit of claim 11, further comprising an addressable line electrically connected to said bipolar resistive change element.

19. The integrated circuit of claim 18, wherein said bipolar resistive change element further comprises a conductive material element interconnecting said addressable line and said bipolar resistive change material.

20. The integrated circuit of claim 11 comprising a three-dimensional structure comprising a fin structure comprising said floating body region, extending substantially perpendicular to, and above a top surface of a substrate.