Three-dimensional vertical NOR flash thing-film transistor strings

• US 10,249,370 B2
• Filed: 08/21/2018
• Issued: 04/02/2019
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Harari, Eli
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US16/107,732
• Publication Number:
  US 20190006009A1
• Time in Patent Office: 224 Days
• Field of Search: 365 46, 365 94, 365100, 365113, 365129, 365148, 365158, 365163, 257 2- 5, 257 9, 257296, 257310, 257379, 257467, 257E2135, 257E31047, 257E27006, 438 29, 438 95, 438 96, 438166, 438135, 438240, 438259, 438365, 438382, 438482, 438486, 438597, 977754
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02595 polycrystalline
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/76892 modifying the pattern
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 : of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 : and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/16 : including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/40117 : the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/4234 : Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6675 : Amorphous silicon or polysilicon transistors
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region

Abstract

A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

Claims

1. A memory structure, comprising:

a storage transistor having a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor having a variable threshold voltage representative of data stored therein;

a word line connected to the gate terminal to provide a control voltage during a read operation;

a bit line connecting the first drain or source terminal to data detection circuitry; and

a source line connected to the second drain or source terminal to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.

2. The memory structure of claim 1, further comprising a pre-charge transistor for charging the capacitance to a predetermined voltage prior to the read operation.

3. The memory structure of claim 1 wherein, during the read operation, the control voltage causes the non-volatile storage transistor to discharge the capacitance, when the sum of the control voltage and the predetermined voltage difference exceeds the variable threshold voltage.

4. The memory structure of claim 1, wherein the capacitance is provided by parasitic capacitance of the source line.

5. The memory structure of claim 1, wherein (i) the storage transistor is formed as a thin-film transistor above a semiconductor substrate having a substantially planar surface, (ii) the first and second drain or source terminals each comprise a conductor extending along a first direction that is substantially orthogonal to the planar surface and (iii) the word line comprise a conductor extending along a second direction substantially parallel to the planar surface.

6. The memory structure of claim 5, wherein the semiconductor substrate comprises circuitry formed therein for supporting a memory circuit.

7. The memory structure of claim 5, wherein the storage transistor is one of a plurality of storage transistors sharing in common the first and second drain or source terminals.

8. The memory structure of claim 7, wherein the gate terminals of the storage transistors are associated with word lines stacked along the first direction isolated from each other by a dielectric material or an air gap.

9. The memory structure of claim 8, wherein the storage transistors are arranged as a three-dimensional array along the first and second directions and along a third direction that is substantially parallel to the planar surface and orthogonal to the second direction.

10. The memory structure of claim 9, wherein the conductors of the word lines associated with the storage transistors are located on a plurality of planes that are each substantially parallel to the planar surface of the semiconductor substrate, and wherein, during programming, the bit lines are each selectively charged to a programming voltage or a program-inhibit voltage, after which programming gate voltages are applied to conductors of the word lines of a selected plane, while conductors of word lines not in the selected plane are held to a non-programming gate voltage.

11. The memory structure of claim 10 wherein, during programming, the bit lines are selectively charged to one of several programming voltages representative of several threshold voltages of a multistate thin film transistor or to a program-inhibit voltage, after which programming gate voltages are applied to conductors of the word lines of the selected plane to program in parallel the several threshold voltages and inhibit further programming of those storage transistors that are read to have reached their predetermined threshold voltage.

12. The memory structure of claim 11, wherein programming or reading of the variable-threshold storage transistors proceeds in parallel for storage transistors associated with different source lines in the three-dimensional array.

13. The memory structure of claim 12 wherein, during the programming or reading of the variable-threshold storage transistors, the capacitances of the different source lines provide currents in the conducting storage transistors, thereby avoiding drawing currents simultaneously from a common voltage source.

14. The memory structure of claim 10, wherein the semiconductor substrate comprises circuitry formed therein for supporting a memory circuit and wherein the memory structure further comprises global source lines, each global source line comprising a conductor extending along the third direction, the global source lines selectively interconnecting the source lines of the storage transistors in the three-dimensional array to the circuitry in the semiconductor substrate.

15. The memory structure of claim 14, wherein the global source lines are provided between the planar surface of the semiconductor substrate and the three-dimensional array of storage transistors.

17. The memory structure of claim 10, the semiconductor substrate comprises circuitry formed therein for supporting a memory circuit and wherein the memory structure further comprising global bit lines comprising conductors extending along the third direction, the global bit lines selectively interconnecting the bit lines of the storage transistors to the circuitry in the semiconductor substrate.

18. The memory structure of claim 17, wherein the global bit lines are provided between the planar surface of the semiconductor substrate and the three-dimensional array of storage transistors.

19. The memory structure of claim 17, wherein the global bit lines are provided above the three-dimensional array of storage transistors.

20. The memory structure of claim 17, further comprising an access select transistor connecting each bit line to one of the global bit lines.

21. The memory structure of claim 17, wherein storage transistors sharing first and second drain and source regions are organized into one or more NOR strings, such that the three-dimensional array comprises columns of NOR strings extending along the second direction and rows of NOR strings extending along the third direction.

22. The memory structure of claim 21, wherein each row of NOR strings is served by first and second global bit lines, wherein the first global bit line connects to the bit lines of every other NOR strings in the row of NOR strings and wherein the second global bit line connects to the bit lines of the row of NOR strings not connected to the first global bit line.

23. The memory structure of claim 22, wherein the NOR strings are isolated from each other by an isolation dielectric or an air gap.

24. The memory structure of claim 21, wherein adjacent NOR strings in a column of NOR strings share a common word line.

25. The memory structure of claim 24, wherein the common word line connects to a gate terminal of a storage transistor in one of the adjacent NOR strings and the gate terminal of a storage transistor of the other one of the adjacent NOR strings.

26. The memory structure of claim 25, wherein the storage transistor further comprises a charge-trapping material adjacent the gate terminal of each storage transistor and wherein the conductor of each word line has an extended portion located between adjacent NOR strings, such that the distance between the extended portions of adjacent conductors of the word lines on the same plane is less than twice as thick as the charge-trapping material.

27. The memory structure of claim 26, wherein each storage transistor further comprises a channel region underneath the charge-trapping material and between the first and second drain and source regions, and wherein the channel region of a storage transistor, the conductor of the word line serving the storage transistor, and the charge-trapping material adjacent the channel region are curved in a predetermined curvature.

28. The memory structure of claim 27, wherein the predetermined curvature is selected such that tunneling of electrons from the channel region into the charge-trapping material is made more efficient during programming due to the predetermined curvature, and tunneling of electrons from the conductor of word line into the charge-trapping material is made less efficient during erasing due to the predetermined curvature.

29. The memory structure of claim 1, wherein the storage transistor further comprises a charge-trapping material adjacent its gate terminal and wherein the charge-trapping material comprises a blocking layer, a storage layer and a tunnel dielectric layer.

30. The memory structure of claim 29, wherein the blocking layer comprises one or more films of aluminum oxide, hafnium oxide, silicon dioxide, silicon nitride or a combination thereof.

31. The memory structure of claim 30, wherein the storage layer comprises one or more films of silicon nitride, silicon-rich oxynitride, conductive nanodots embedded in a dielectric film, isolated floating gates or a combination thereof.

32. The memory structure of claim 30, wherein the tunnel dielectric layer comprises a silicon dioxide film, or a silicon oxide-silicon nitride-silicon oxide (“

ONO”

) triple-layer.

33. The memory structure of claim 29, wherein the charge-trapping material is selected such that the storage transistor has a data retention time exceeding one minute and an endurance exceeding one hundred thousand cycles.

34. The memory structure of claim 29, wherein the tunnel dielectric layer is sufficiently thin to permit substantially direct tunneling into and reverse direct tunneling out of the storage layer.

35. The memory structure of claim 8, wherein the storage transistors are organized as individually addressable storage transistors of one or more NOR strings.

36. The memory structure of claim 35, wherein each NOR string further comprise a pre-charge transistor coupled between the first and second drain or source terminals, and wherein, when the pre-charge transistor is conducting, the pre-charge transistor substantially charges the source line to a voltage of the bit line.

37. The memory structure of claim 36, wherein the capacitance is charged to a predetermined voltage prior to the read operation, and wherein the capacitance is discharged when the sum of a read voltage placed on the gate terminal and the predetermined voltage difference exceeds the variable threshold voltage.

38. The memory structure of claim 35, wherein the source line is rendered electrically floating when all the storage transistors are non-conducting and wherein the capacitance of the source line, when charged, serves as a virtual voltage source.

39. The memory structure of claim 38, further comprising one or more conductors coupled to the source line, the conductors providing additional capacitance to the capacitance of the source line.

40. The memory structure of claim 5, the storage transistor further comprises a channel region provided between the conductors of the first and the second drain or source terminals.

41. The memory structure of claim 40, wherein the conductors of the first and second drain or source terminals comprise a semiconductor material of a first conductivity and wherein the channel region comprise a semiconductor material of a second conductivity.

42. The memory structure of claim 5, wherein circuitry for supporting a memory circuit are formed in the semiconductor substrate, the circuitry comprises a voltage drop detector selectably connected to the storage transistor to detect a voltage drop resulting from the storage transistor being rendered conducting during a read operation.

43. The memory structure of claim 1, wherein the storage transistor further comprises a charge-trapping material adjacent the gate terminal and wherein the variable threshold of the storage transistor is achieved by storing charge in the charge-trapping material using a channel hot-electron injection programming technique.

44. The memory structure of claim 43, wherein the storage transistor further comprises a channel region between the first and second drain or source terminals and wherein the charge-trapping material is between the gate terminal and a portion of the channel region.

45. The memory structure of claim 9, wherein each storage transistor in the three-dimensional array stores more than one bit of data.

46. The memory structure of claim 45, wherein the stored data of each storage transistor determines its threshold voltage.

47. The memory structure of claim 46, further comprising a plurality of reference storage transistors in the three-dimensional storage array each having a threshold voltage representing a programmable reference voltage.

48. The memory structure of claim 47, wherein the semiconductor substrate comprises circuitry formed therein for supporting a memory circuit and wherein the supporting circuitry in the semiconductor substrate detects the stored data of a storage transistor by comparing a threshold voltage of the storage transistor with a threshold voltage in each of a plurality of the programmable reference storage transistors.

49. The memory structure of claim 47, wherein the supporting circuitry in the semiconductor substrate compares a rate of discharge in the storage transistor with rates of discharge of the programmable reference storage transistors.

16. The memory structure of 14, further comprising an access select transistor connecting each source line to one of the global source lines.