Control circuit, semiconductor storage device, and method of controlling semiconductor storage device

• US 10,249,371 B2
• Filed: 09/28/2017
• Issued: 04/02/2019
• Est. Priority Date: 11/01/2016
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Maeda, Masazumi
• Primary Examiner(s): Bui, Tha-O H
• Assistant Examiner(s): Lozada, Alfredo Bermudez
• Application Number:
  US15/718,029
• Publication Number:
  US 20180122480A1
• Time in Patent Office: 551 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2216/24 Nonvolatile memory in which programming can be carried out in one memory bank or array whilst a word or sector in another bank or array is being erased simultaneously
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches

Abstract

A control circuit that controls a memory including a storage region and a redundant region, the control circuit includes a detector that detects a defective block in the memory, and a controller that switches, when the detector has detected the defective block, a data storage scheme of the first block detected as the defective block from a first storage scheme to a second storage scheme in which the number of bits of data to be stored in each of memory elements is smaller than the number of bits of data to be stored in each of the memory elements in the first storage scheme, and that stores a portion of data stored in the first block in the first storage scheme to be stored in the first block in the second storage scheme.

Claims

1. A control circuit that controls a memory including a storage region and a redundant region, the control circuit comprising:

a detector that detects a defective block in the memory; and

a controller that switches, when the detector has detected the defective block, a data storage scheme of the first block detected as the defective block from a first storage scheme to a second storage scheme in which the number of bits of data to be stored in each of memory elements is smaller than the number of bits of data to be stored in each of the memory elements in the first storage scheme, and that stores a portion of data stored in the first block in the first storage scheme to be stored in the first block in the second storage scheme and stores the remaining portion of the data stored in the first block in the first storage scheme to be stored in a second block of the redundant region,

the controller writes all the data stored in the first block in the first storage scheme in the second block of the redundant region and a third block of the redundant region, switches the data storage scheme of the first block from the first storage scheme to the second storage scheme, and writes back data written in the third block of the redundant region to the first block in the second storage scheme after the switching of the data storage scheme.

2. The control circuit according to claim 1, wherein the number of bits to be stored in each of the memory elements in the second storage scheme is smaller by 1 bit than the number of bits to be stored in each of the memory elements in the first storage scheme.

3. The control circuit according to claim 1, wherein data of 2 bits is to be stored in each of the memory elements in the first storage scheme, while data of 1 bit is to be stored in each of the memory elements in the second storage scheme.

4. The control circuit according to claim 1, wherein data of 3 bits is to be stored in each of the memory elements in the first storage scheme, while data of 2 bits is to be stored in each of the memory elements in the second storage scheme.

5. The control circuit according to claim 1,

wherein a storage capacity of each of blocks of the redundant region in the first storage scheme is equal to a half of a storage capacity of each of blocks of the storage region in the first storage scheme, and

wherein the controller stores data to be stored in the blocks of the redundant region in the first storage scheme.

6. The control circuit according to claim 1, wherein the memory elements of the memory are nonvolatile memory elements.

7. The control circuit according to claim 1, wherein when the detector has detected, as the defective block, the first block storing the data in the switched second storage scheme, the controller stores all the data stored in the first block to be stored in a block of the redundant region and stores the first block to be unusable.

8. The control circuit according to claim 1, wherein when the detector has detected, as the defective block, the first block storing the data in the switched second storage scheme, the controller switches the data storage scheme of the first block from the second storage scheme to a third storage scheme in which the number of bits of data to be stored in each of the memory elements is smaller than the number of bits of data to be stored in each of the memory elements in the second storage scheme, and the controller stores a portion of the data stored in the first block in the second storage scheme to be stored in the first block in the third storage scheme and stores the remaining portion of the data stored in the first block in the second storage scheme to be stored in a third block of the redundant region.

9. The control circuit according to claim 8, wherein data of 3 bits is to be stored in each of the memory elements in the first storage scheme, data of 2 bits is to be stored in each of the memory elements in the second storage scheme, and data of 1 bit is to be stored in each of the memory elements in the third storage scheme.

10. The control circuit according to claim 8, wherein a storage capacity of each of blocks of the redundant region in the first storage scheme is equal to one fourth of a storage capacity of each of blocks of the storage region in the first storage scheme.

11. The control circuit according to claim 8, wherein when the detector has detected, as the defective block, the first block storing the data in the switched third storage scheme, the controller stores all the data stored in the first block to be stored in a block of the redundant region and stores the first block to be unusable.

12. A semiconductor storage device comprising:

a memory that includes a storage region and a redundant region; and

a control circuit that controls the memory, the control circuit includes

a detector that detects a defective block in the memory, and

a controller that switches, when the detector has detected the defective block, a data storage scheme of the first block detected as the defective block from a first storage scheme to a second storage scheme in which the number of bits of data to be stored in each of memory elements is smaller than the number of bits of data to be stored in each of the memory elements in the first storage scheme, and that stores a portion of data stored in the first block in the first storage scheme to be stored in the first block in the second storage scheme and stores the remaining portion of the data stored in the first block in the first storage scheme to be stored in a second block of the redundant region,

the controller writes all the data stored in the first block in the first storage scheme in the second block of the redundant region and a third block of the redundant region, switches the data storage scheme of the first block from the first storage scheme to the second storage scheme, and writes back data written in the third block of the redundant region to the first block in the second storage scheme after the switching of the data storage scheme.

13. A method of controlling a semiconductor storage device including a memory that includes a storage region and a redundant region, comprising:

when a control circuit of the semiconductor storage device determines whether or not the control circuit has detected a defective block in the memory, and the control circuit has detected the defective block, causing the control circuit to switch a data storage scheme of the first block detected as the defective block from a first storage scheme to a second storage scheme in which the number of bits of data to be stored in each of memory elements is smaller than the number of bits of data to be stored in each of the memory elements in the first storage scheme;

causing the control circuit to store a portion of data stored in the first block in the first storage scheme to be stored in the first block in the second storage scheme; and

causing the control circuit to store the remaining portion of the data stored in the first block in the first storage scheme to be stored in a second block of the redundant region,

when the control circuit has detected the defective block, causing the control circuit to write all the data stored in the first block in the first storage scheme in the second block of the redundant region and a third block of the redundant region;

causing, after the writing, the control circuit to switch the data storage scheme of the first block from the first storage scheme to the second storage scheme; and

causing, after the switching of the data storage scheme, the control circuit to write back data written in the third block of the redundant region to the first block in the second storage scheme.