Method of forming vertical field effect transistors with different gate lengths and a resulting structure

• US 10,249,538 B1
• Filed: 10/03/2017
• Issued: 04/02/2019
• Est. Priority Date: 10/03/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Qi, Yi, Lo, Hsien-Ching, Peng, Jianwei, Hong, Wei, Shen, Yanping, Shi, Yongjun, Zang, Hui, Xie, Ruilong, Cheng, Kangguo, Yamashita, Tenko, Yeh, Chun-chen
• Primary Examiner(s): Gheyas, Syed I
• Application Number:
  US15/723,472
• Publication Number:
  US 20190103319A1
• Time in Patent Office: 546 Days
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/3213 Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.

Claims

1. A method comprising:

forming, on a semiconductor substrate, a first lower source/drain region with a first semiconductor fin extending vertically upward from a top surface of the first lower source/drain region and a second lower source/drain region with a second semiconductor fin extending upward from a top surface of the second lower source/drain region,

wherein a height of the top surface of the first lower source/drain region as measured from a planar bottom surface of the semiconductor substrate is less than a height of the top surface of the second lower source/drain region as measured from the planar bottom surface of the semiconductor substrate such that the top surface of the first lower source/drain region is below a level of the top surface of the second lower source/drain region, and

wherein the first semiconductor fin and the second semiconductor fin are patterned from a monocrystalline epitaxial semiconductor layer and are physically separated from the semiconductor substrate by the first lower source/drain region and the second lower source/drain region, respectively; and

,

forming a first transistor with the first lower source/drain region and a second transistor with the second lower source/drain region.

2. The method of claim 1,

wherein the forming of the first transistor and the second transistor further comprises:

forming a first lower spacer above the first lower source/drain region and positioned laterally adjacent to the first semiconductor fin and a second lower spacer above the second lower source/drain region and positioned laterally adjacent to the second semiconductor fin;

forming a first gate above the first lower spacer and positioned laterally adjacent to the first semiconductor fin and a second gate above the second lower spacer and positioned laterally adjacent to the second semiconductor fin;

forming a first upper spacer above the first gate and positioned laterally adjacent to the first semiconductor fin and a second upper spacer above the second gate and positioned laterally adjacent to the second semiconductor fin; and

forming a first upper source/drain region above the first upper spacer and immediately adjacent to a top of the first semiconductor fin and a second upper source/drain region above the second upper spacer and immediately adjacent to a top of the second semiconductor fin,

wherein a top surface of the first lower spacer is below a level of a top surface of the second lower spacer and the first gate and the second gate have co-planar top surfaces such that the first gate has a first gate length and the second gate has a second gate length that is less than the first gate length and such that the first transistor has a first threshold voltage and the second transistor has a second threshold voltage that is less than the first threshold voltage.

3. The method of claim 2, further comprising, before the forming of the first lower source/drain region and the second lower source/drain region:

providing the semiconductor substrate;

recessing a first portion of the semiconductor substrate such that the semiconductor substrate has a recessed first portion and an unrecessed second portion;

conformally depositing a sacrificial layer on the semiconductor substrate;

depositing the monocrystalline epitaxial semiconductor layer on the sacrificial layer;

planarizing the monocrystalline epitaxial semiconductor layer;

patterning the monocrystalline epitaxial semiconductor layer into the first semiconductor fin and the second semiconductor fin, the first semiconductor fin being above the recessed first portion of the semiconductor substrate and the second semiconductor fin being above the unrecessed second portion of the semiconductor substrate such that the first semiconductor fin is taller than the second semiconductor fin; and

etching the sacrificial layer to expose a top surface of the recessed first portion of the semiconductor substrate and a top surface of the unrecessed second portion of the semiconductor substrate,

wherein the forming of the first lower source/drain region and the second lower source/drain region comprises epitaxially depositing semiconductor material on the top surface of the recessed first portion of the semiconductor substrate adjacent to the first semiconductor fin to form the first lower source/drain region and on the top surface of the unrecessed second portion of the semiconductor substrate adjacent to the second semiconductor fin to form the second lower source/drain region.

4. The method of claim 2, further comprising, before the forming of the first lower source/drain region and the second lower source/drain region:

providing the semiconductor substrate;

depositing a sacrificial layer on the semiconductor substrate;

recessing a first portion of the sacrificial layer such that the sacrificial layer has a recessed first portion and an unrecessed second portion;

depositing the monocrystalline epitaxial semiconductor layer on the sacrificial layer;

planarizing the monocrystalline epitaxial semiconductor layer;

patterning the monocrystalline epitaxial semiconductor layer into the first semiconductor fin and the second semiconductor fin, the first semiconductor fin being above the recessed first portion of the sacrificial layer and the second semiconductor fin being above the unrecessed second portion of the sacrificial layer such that the first semiconductor fin is taller than the second semiconductor fin; and

etching the recessed first portion and the unrecessed second portion of the sacrificial layer to expose the semiconductor substrate,

wherein the forming of the first lower source/drain region and the second lower source/drain region comprises epitaxially depositing semiconductor material on the semiconductor substrate adjacent to the first semiconductor fin to form the first lower source/drain region and on the semiconductor substrate adjacent to the second semiconductor fin to form the second lower source/drain region.

5. The method of claim 1, further comprising forming a trench isolation region between the first lower source/drain region and the second lower source/drain region.

6. A method comprising:

forming a sacrificial layer on a semiconductor substrate such that the sacrificial layer has a first portion and a second portion, wherein a height of a top surface of the first portion of the sacrificial layer as measured from a planar bottom surface of the semiconductor substrate is less than a height of a top surface of the second portion of the sacrificial layer as measured from the planar bottom surface of the semiconductor substrate such that the top surface of the first portion of the sacrificial layer is below a level of the top surface of the second portion of the sacrificial layer;

forming a semiconductor layer on the sacrificial layer;

planarizing the semiconductor layer;

patterning the semiconductor layer into a first semiconductor fin and a second semiconductor fin, the first semiconductor fin being above the first portion of the sacrificial layer and the second semiconductor fin being above the second portion of the sacrificial layer such that the first semiconductor fin is taller than the second semiconductor fin;

etching the sacrificial layer to expose the semiconductor substrate;

forming a first lower source/drain region on the semiconductor substrate adjacent to the first semiconductor fin and a second lower source/drain region on the semiconductor substrate adjacent to the second semiconductor fin such that a top surface of the first lower source/drain region is below a level of a top surface of the second lower source/drain region; and

forming a first transistor with the first lower source/drain region and the first semiconductor fin and a second transistor with the second lower source/drain region and the second semiconductor fin.

7. The method of claim 6, the semiconductor substrate and the semiconductor layer comprising silicon and the sacrificial layer comprising any of silicon germanium, silicon germanium carbide and boron-doped silicon germanium.

8. The method of claim 6, wherein the forming of the first transistor and the second transistor comprises:

forming a first lower spacer above the first lower source/drain region and positioned laterally adjacent to the first semiconductor fin and a second lower spacer above the second lower source/drain region and positioned laterally adjacent to the second semiconductor fin;

forming a first gate above the first lower spacer and positioned laterally adjacent to the first semiconductor fin and a second gate above the second lower source/drain region and positioned laterally adjacent to the second semiconductor fin;

forming a first upper spacer above the first gate and positioned laterally adjacent to the first semiconductor fin and a second upper spacer above the second gate and positioned laterally adjacent to the second semiconductor fin; and

forming a first upper source/drain region above the first upper spacer and immediately adjacent to a top of the first semiconductor fin and a second upper source/drain region above the second upper spacer and immediately adjacent to a top of the second semiconductor fin,

wherein a top surface of the first lower spacer is below a level of a top surface of the second lower spacer and the first gate and the second gate have co-planar top surfaces such that the first gate has a first gate length and the second gate has a second gate length that is less than the first gate length and such that the first transistor has a first threshold voltage and the second transistor has a second threshold voltage that is less than the first threshold voltage.

9. The method of claim 6,

wherein the method further comprises, before the forming of the sacrificial layer, recessing a first portion of the semiconductor substrate such that the semiconductor substrate comprises a recessed first portion and an unrecessed second portion, and

wherein the forming of the sacrificial layer comprises conformally depositing the sacrificial layer onto the semiconductor substrate such that the sacrificial layer has an essentially uniform thickness and such that the first portion of the sacrificial layer is on the recessed first portion of the semiconductor substrate and the second portion of the sacrificial layer is on the unrecessed second portion of the semiconductor substrate.

10. The method of claim 6,

wherein the semiconductor substrate has a planar top surface, and

wherein the forming of the sacrificial layer comprises:

depositing the sacrificial layer onto the planar top surface of the semiconductor substrate such that the sacrificial layer has a planar bottom surface and an essentially uniform thickness; and

after the depositing of the sacrificial layer, recessing the first portion of the sacrificial layer such that the sacrificial layer has a recessed first portion with a first thickness and an unrecessed second portion with a second thickness that is greater than the first thickness.

11. The method of claim 6, the first lower source/drain region and the second lower source/drain region being formed using a self-limiting epitaxial deposition process.

12. The method of claim 6, further comprising:

forming anchor regions attached to the first semiconductor fin and the second semiconductor fin and extending vertically through the sacrificial layer and into the semiconductor substrate,

wherein the etching of the sacrificial layer to expose the semiconductor substrate comprises performing a selective isotropic etch process to completely remove the sacrificial layer from below the first semiconductor fin and the second semiconductor fin, and

wherein the anchor regions provide support for the first semiconductor fin and the second semiconductor fin until the first lower source/drain region and the second lower source/drain region are formed.

13. The method of claim 6, wherein the etching of the sacrificial layer to expose the semiconductor substrate comprises performing a selective anisotropic etch process so that fin-shaped sections of the sacrificial layer remain aligned below the first semiconductor fin and the second semiconductor fin, respectively.

14. The method of claim 6, further comprising forming a trench isolation region between the first lower source/drain region and the second lower source/drain region.

15. A structure comprising:

a semiconductor substrate;

a first transistor comprising a first lower source/drain region on the semiconductor substrate and a first semiconductor fin extending vertically upward from a top surface of the first lower source/drain region; and

a second transistor comprising a second lower source/drain region on the semiconductor substrate and a second semiconductor fin extending upward from a top surface of the second lower source/drain region,

wherein a height of the top surface of the first lower source/drain region as measured from a planar bottom surface of the semiconductor substrate is less than a height of the top surface of the second lower source/drain region as measured from the planar bottom surface of the semiconductor substrate such that the top surface of the first lower source/drain region is below a level of the top surface of the second lower source/drain region, and

wherein the first semiconductor fin and the second semiconductor fin comprise monocrystalline epitaxial semiconductor material and are physically separated from the semiconductor substrate by the first lower source/drain region and the second lower source/drain region, respectively.

16. The structure of claim 15,

wherein the first transistor further comprises:

a first upper source/drain region, wherein the first semiconductor fin extends vertically between the first lower source/drain region and the first upper source/drain region;

a first lower spacer above the first lower source/drain region and positioned laterally adjacent to the first semiconductor fin;

a first gate above the first lower spacer and positioned laterally adjacent to the first semiconductor fin; and

a first upper spacer between the first gate and the first upper source/drain region and positioned laterally adjacent to the first semiconductor fin,

wherein the second transistor comprises;

a second upper source/drain region, wherein the second semiconductor fin extends vertically between the second lower source/drain region and the second upper source/drain region, the second semiconductor fin being shorter than the first semiconductor fin;

a second lower spacer above the second lower source/drain region and positioned laterally adjacent to the second semiconductor fin, wherein a top surface of the first lower spacer is below a level of a top surface of the second lower spacer;

a second gate above the second lower spacer and positioned laterally adjacent to the second semiconductor fin, the first gate and the second gate having co-planar top surfaces such that the first gate has a first gate length and the second gate has a second gate length that is less than the first gate length; and

a second upper spacer between the second gate and the second upper source/drain region and positioned laterally adjacent to the second semiconductor fin, and

wherein the structure further comprises a trench isolation region between the first lower source/drain region and the second lower source/drain region.

17. The structure of claim 15, wherein the first transistor has a higher threshold voltage than the second transistor.

18. The structure of claim 15,

wherein the semiconductor substrate has a recessed first portion and an unrecessed second portion,

wherein the first lower source/drain region is above the recessed first portion,

wherein the second lower source/drain region is above the unrecessed second portion, and

wherein the first lower source/drain region and the second lower source/drain region have approximately equal thicknesses.

19. The structure of claim 15,

wherein the semiconductor substrate has a planar top surface,

wherein the first lower source/drain region has a first thickness, and

wherein the second lower source/drain region has a second thickness that is greater than the first thickness.