Method of forming vertical field effect transistors with different gate lengths and a resulting structure
First Claim
1. A method comprising:
- forming, on a semiconductor substrate, a first lower source/drain region with a first semiconductor fin extending vertically upward from a top surface of the first lower source/drain region and a second lower source/drain region with a second semiconductor fin extending upward from a top surface of the second lower source/drain region,wherein a height of the top surface of the first lower source/drain region as measured from a planar bottom surface of the semiconductor substrate is less than a height of the top surface of the second lower source/drain region as measured from the planar bottom surface of the semiconductor substrate such that the top surface of the first lower source/drain region is below a level of the top surface of the second lower source/drain region, andwherein the first semiconductor fin and the second semiconductor fin are patterned from a monocrystalline epitaxial semiconductor layer and are physically separated from the semiconductor substrate by the first lower source/drain region and the second lower source/drain region, respectively; and
,forming a first transistor with the first lower source/drain region and a second transistor with the second lower source/drain region.
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Accused Products
Abstract
Disclosed is a method of forming a structure with multiple vertical field effect transistors (VFETs). In the method, lower source/drain regions are formed on a substrate such that semiconductor fins extend vertically above the lower source/drain regions. Lower spacers are formed on the lower source/drain regions and positioned laterally adjacent to the semiconductor fins. Gates, having co-planar top surfaces, are formed on the lower spacers and positioned laterally adjacent to the semiconductor fins. However, process steps are performed prior to gate formation to ensure that the top surfaces of the lower source/drain region and lower spacer of a first VFET are below the levels of the top surfaces of the lower source/drain region and lower spacer, respectively, of a second VFET. As a result, the first VFET will have a longer gate, higher threshold voltage and lower switching speed. Also disclosed is the structure formed according to the method.
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Citations
19 Claims
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1. A method comprising:
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forming, on a semiconductor substrate, a first lower source/drain region with a first semiconductor fin extending vertically upward from a top surface of the first lower source/drain region and a second lower source/drain region with a second semiconductor fin extending upward from a top surface of the second lower source/drain region, wherein a height of the top surface of the first lower source/drain region as measured from a planar bottom surface of the semiconductor substrate is less than a height of the top surface of the second lower source/drain region as measured from the planar bottom surface of the semiconductor substrate such that the top surface of the first lower source/drain region is below a level of the top surface of the second lower source/drain region, and wherein the first semiconductor fin and the second semiconductor fin are patterned from a monocrystalline epitaxial semiconductor layer and are physically separated from the semiconductor substrate by the first lower source/drain region and the second lower source/drain region, respectively; and
,forming a first transistor with the first lower source/drain region and a second transistor with the second lower source/drain region. - View Dependent Claims (2, 3, 4, 5)
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6. A method comprising:
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forming a sacrificial layer on a semiconductor substrate such that the sacrificial layer has a first portion and a second portion, wherein a height of a top surface of the first portion of the sacrificial layer as measured from a planar bottom surface of the semiconductor substrate is less than a height of a top surface of the second portion of the sacrificial layer as measured from the planar bottom surface of the semiconductor substrate such that the top surface of the first portion of the sacrificial layer is below a level of the top surface of the second portion of the sacrificial layer; forming a semiconductor layer on the sacrificial layer; planarizing the semiconductor layer; patterning the semiconductor layer into a first semiconductor fin and a second semiconductor fin, the first semiconductor fin being above the first portion of the sacrificial layer and the second semiconductor fin being above the second portion of the sacrificial layer such that the first semiconductor fin is taller than the second semiconductor fin; etching the sacrificial layer to expose the semiconductor substrate; forming a first lower source/drain region on the semiconductor substrate adjacent to the first semiconductor fin and a second lower source/drain region on the semiconductor substrate adjacent to the second semiconductor fin such that a top surface of the first lower source/drain region is below a level of a top surface of the second lower source/drain region; and forming a first transistor with the first lower source/drain region and the first semiconductor fin and a second transistor with the second lower source/drain region and the second semiconductor fin. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. A structure comprising:
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a semiconductor substrate; a first transistor comprising a first lower source/drain region on the semiconductor substrate and a first semiconductor fin extending vertically upward from a top surface of the first lower source/drain region; and a second transistor comprising a second lower source/drain region on the semiconductor substrate and a second semiconductor fin extending upward from a top surface of the second lower source/drain region, wherein a height of the top surface of the first lower source/drain region as measured from a planar bottom surface of the semiconductor substrate is less than a height of the top surface of the second lower source/drain region as measured from the planar bottom surface of the semiconductor substrate such that the top surface of the first lower source/drain region is below a level of the top surface of the second lower source/drain region, and wherein the first semiconductor fin and the second semiconductor fin comprise monocrystalline epitaxial semiconductor material and are physically separated from the semiconductor substrate by the first lower source/drain region and the second lower source/drain region, respectively. - View Dependent Claims (16, 17, 18, 19)
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Specification