Cavity formation using sacrificial material

• US 10,249,576 B2
• Filed: 10/26/2017
• Issued: 04/02/2019
• Est. Priority Date: 05/15/2015
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Petzold, David T., Whitefield, David Scott
• Primary Examiner(s): Vuong, Quochien B
• Application Number:
  US15/794,747
• Publication Number:
  US 20180076222A1
• Time in Patent Office: 523 Days
• Field of Search: 455 73, 455 78, 455 84, 438143, 438149, 438238, 438240, 438241, 438310, 438311, 438329, 438359
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2221/68318 Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 : being square
• CPC Class Codes: H01L 2224/06135 : Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/5283 : Cross-sectional geometry
• CPC Class Codes: H01L 23/535 : including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 29/0649 : Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66772 : Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/786 : Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78603 : characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78648 : arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1421 : RF devices
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H03H 9/02566 : of semiconductor substrates
• CPC Class Codes: H03H 9/24 : Constructional features of resonators of material which is not piezoelectric, electrostrictive, or magnetostrictive
• CPC Class Codes: H04B 1/40 : Circuits
• CPC Class Codes: H04B 1/44 : Transmit/receive switching
• CPC Class Codes: H10N 39/00 : Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00

Abstract

A method for fabricating a semiconductor device involves providing a semiconductor substrate, forming an oxide layer in the semiconductor substrate, forming a transistor device over the oxide layer, removing at least part of a backside of the semiconductor substrate, applying a sacrificial material below the oxide layer, covering the sacrificial material with an interface material, and removing at least a portion of the sacrificial material to form a cavity at least partially covered by the interface layer.

Claims

1. A method for fabricating a semiconductor device, the method comprising:

providing a semiconductor substrate;

forming an oxide layer in the semiconductor substrate;

forming a transistor device over the oxide layer;

removing at least part of a backside of the semiconductor substrate;

applying a sacrificial material below the oxide layer;

covering the sacrificial material with an interface material; and

removing at least a portion of the sacrificial material to form a cavity at least partially covered by the interface material.

2. The method of claim 1 further comprising applying a substrate contact layer to a backside of the oxide layer, the substrate contact layer being at least partially exposed in the cavity after said removing the at least a portion of the sacrificial material.

3. The method of claim 1 further comprising applying a replacement substrate layer to the interface material to provide mechanical stability for the semiconductor device.

4. The method of claim 1 wherein said applying the sacrificial material involves forming a channel of the sacrificial material leading to a die boundary associated with the semiconductor device.

5. The method of claim 4 wherein said removing the at least a portion of the sacrificial material is performed at least partially through the channel.

6. The method of claim 1 wherein said removing the at least a portion of the sacrificial material involves evaporating the at least a portion of the sacrificial material.

7. The method of claim 1 further comprising removing a handle wafer from a front-side of a passivation layer disposed over the transistor device.

8. The method of claim 1 wherein the sacrificial material comprises nitride.

9. A semiconductor device comprising:

a transistor device implemented over an oxide layer;

a patterned form of sacrificial material disposed below the oxide layer and the transistor device; and

an interface layer covering at least a portion of a backside of the patterned form of sacrificial material.

10. The semiconductor device of claim 9 wherein the patterned form of sacrificial material includes a channel leading to an edge of a die associated with the semiconductor device.

11. The semiconductor device of claim 10 wherein the patterned form of sacrificial material is patterned to allow for removal thereof through evaporation by applying heat to the channel.

12. The semiconductor device of claim 9 further comprising a substrate contact layer disposed on a backside of the oxide layer in physical contact with the patterned form of sacrificial material.

13. The semiconductor device of claim 9 further comprising a replacement substrate layer applied to the interface layer, the replacement substrate layer providing mechanical stability for the semiconductor device.

14. The semiconductor device of claim 9 wherein the transistor device is part of a switching device.

15. The semiconductor device of claim 9 wherein the patterned form of sacrificial material comprises low-density oxide.

16. A semiconductor die comprising:

a semiconductor substrate;

an oxide layer disposed above the semiconductor substrate;

a transistor device implemented over the oxide layer; and

an interface layer disposed between the oxide layer and the semiconductor substrate, the interface layer having a cavity formed therein that is connected to a channel that leads to an edge of the semiconductor die.

17. The semiconductor die of claim 16 wherein the channel is patterned to allow for removal of sacrificial material disposed in a volume of the cavity to thereby form the cavity.

18. The semiconductor die of claim 16, wherein the channel is patterned to allow for application of head thereto from the edge of the semiconductor die to thereby evaporate sacrificial material disposed therein.

19. The semiconductor die of claim 16 further comprising a substrate contact layer disposed on a backside of the oxide layer and at least partially exposed within the cavity.

20. The semiconductor die of claim 16 wherein the transistor device is part of a switching device.