Method of forming metal interconnection and method of fabricating semiconductor apparatus using the method

• US 10,249,577 B2
• Filed: 04/27/2017
• Issued: 04/02/2019
• Est. Priority Date: 05/17/2016
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holding B.V. (ASM International NV)
• Inventors: Lee, Choong Man, Yoo, Yong Min, Kim, Young Jae, Chun, Seung Ju, Kim, Sun Ja
• Primary Examiner(s): Smith, Bradley
• Application Number:
  US15/499,647
• Publication Number:
  US 20170338192A1
• Time in Patent Office: 705 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02074 the processing being a planarization of conductive layers
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02219 the compound comprising silicon and nitrogen
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26

Abstract

A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in the trench, filling a metal on the barrier layer, planarizing the metal, and forming a capping layer on the planarized metal, wherein the capping layer includes at least two layers.

Claims

1. A method of forming a metal interconnection, the method comprising:

depositing a low-k dielectric layer;

forming a trench in the low-k dielectric layer;

forming a barrier layer in the trench;

filling a metal on the barrier layer;

planarizing the metal; and

forming a capping layer on the planarized metal,

wherein the capping layer comprises at least two layers and has a thickness equal to or less than 100 Å

,

wherein the forming of the capping layer comprises depositing a first nitride layer and a second nitride layer, and

wherein the depositing of the first nitride layer and the second nitride layer comprises;

depositing an aluminum nitride (AlN) layer; and

depositing a silicon nitride (SiN) layer,

wherein a ratio of a thickness of the AIN layer to a thickness of the SiN layer ranges from 1;

15 to 1;

2, and

wherein, when the capping layer comprising the AlN layers and SiN layer is exposed for 17 hours at a temperature of 85°

C. and a humidity of 85%, a change in strees of a thin film is equal to or less than 50 MPa.

2. The method of claim 1, wherein the AlN layer is formed by using a plasma-enhanced atomic layer deposition (PEALD) method.

3. The method of claim 2, wherein the depositing of the AlN layer comprises a plurality of cycles,

wherein each of the plurality of cycles comprises:

supplying an aluminum (Al) source gas;

supplying a purge gas;

supplying a reactive gas and activating the reactive gas by using plasma; and

supplying the purge gas,

wherein the purge gas is continuously supplied to a reaction space during the plurality of cycles.

4. The method of claim 3, wherein the Al source gas comprises trimethyl aluminum (Al(CH₃)₃ or TMA), and the reactive gas comprises a gas mixture of nitrogen and hydrogen.

5. The method of claim 1, wherein the SiN layer is formed by using a pulsed plasma-enhanced chemical vapor deposition (P-PECVD) method.

6. The method of claim 1, wherein a thickness of the SiN layer is at least 30 Å

.

7. The method of claim 1, wherein the first nitride layer and the second nitride layer are formed in-situ in the same reactor.

8. A method of forming a metal interconnection, the method comprising:

depositing a low-k dielectric layer;

forming a trench in the low-k dielectric layer;

forming a barrier layer in the trench;

filling a metal on the barrier layer;

planarizing the metal; and

forming a capping layer on the planarized metal,

wherein the capping layer comprises at least two layers and has a thickness equal to or less than 100 Å

,

wherein the forming of the capping layer comprises depositing a first nitride layer and a second nitride layer,

wherein the depositing of the first nitride layer and the second nitride layer comprises;

depositing an aluminum nitride (AlN) layer; and

depositing a silicon nitride (SiN) layer,

wherein the SiN layer is formed by using a pulsed plasma-enhanced chemical vapor deposition (P-PECVD) method,

wherein the depositing of the SiN layer comprises a plurality of cycles,

wherein each of the plurality of cycles comprises;

supplying a silicon (Si) source gas;

supplying a purge gas;

supplying a reactive gas and activating the reactive gas by using plasma; and

supplying the purge gas, and

wherein the reactive gas, the purge gas, and the plasma are continuously supplied to a reaction space during the plurality of cycles.

9. The method of claim 8, wherein the Si source gas comprises Si and H elements.

10. The method of claim 9, wherein the Si source gas comprises at least one from among SiH₄, bis(diethylamino) silane (BDEAS), and diisopropylamino silane (DIPAS).

11. The method of claim 8, wherein the reactive gas comprises a gas mixture of nitrogen and hydrogen.

12. A method of forming a metal interconnection, the method comprising:

depositing a low-k dielectric layer;

forming a trench in the low-k dielectric layer;

forming a barrier layer in the trench;

filling a metal on the barrier layer;

planarizing the metal; and

forming a capping layer on the planarized metal, wherein the capping layer comprises at least two layers and has a thickness equal to or less than 100 Å

,

wherein the forming of the capping layer comprises depositing a first nitride layer and a second nitride layer,

wherein the depositing of the first nitride layer and the second nitride layer comprises;

depositing an aluminum nitride (AlN) layer; and

depositing a silicon nitride (SiN) layer,

wherein the SiN layer is formed by using a pulsed plasma-enhanced chemical vapor deposition (P-PECVD) method,

wherein the method further comprises performing plasma processing before the deposition of the first nitride layer and the second nitride layer,

wherein performing the plasma processing comprises at least one cycle,

wherein each of the at least one cycle comprises;

supplying a nitrogen-containing gas;

activating the nitrogen-containing gas by using plasma; and

supplying a purge gas, and

wherein a metal oxide on the metal is reduced into a metal during the cycle.

13. A method of forming a metal interconnection, the method comprising:

depositing a low-k dielectric layer;

forming a trench in the low-k dielectric layer;

forming a barrier layer in the trench;

filling a metal on the barrier layer;

planarizing the metal; and

forming a capping layer on the planarized metal,

wherein the capping layer comprises at least two layers and has a thickness equal to or less than 100 Å

,

wherein the forming of the capping layer comprises depositing a first nitride layer and a second nitride layer,

wherein the depositing of the first nitride layer and the second nitride layer comprises;

depositing an aluminum nitride (AlN) layer; and

depositing a silicon nitride (SiN) layer,

wherein the SiN layer is formed by using a pulsed plasma-enhanced chemical vapor deposition (P-PECVD) method, and,

wherein the forming of the capping layer is performed at a temperature ranging from about 250°

C. to about 350°

C.

14. A method of forming a metal interconnection, the method comprising:

depositing a low-k dielectric layer;

forming a trench in the low-k dielectric layer;

forming a barrier layer in the trench;

filling a metal on the barrier layer;

planarizing the metal; and

forming a capping layer on the planarized metal,

wherein the capping layer comprises at least two layers and has a thickness equal to or less than 100 Å

,

wherein the forming of the capping layer comprises depositing a first nitride layer and a second nitride layer,

wherein the depositing of the first nitride layer and the second nitride layer comprises;

depositing an aluminum nitride (AlN) layer; and

depositing a silicon nitride (SiN) layer,

wherein the SiN layer is formed by using a plasma-enhanced atomic layer deposition (PEALD) method, and

wherein a ratio of power of plasma supplied during the depositing of the AlN layer to power of plasma supplied during the depositing of the SiN layer ranges from about 10;

1 to 8;

1.

15. A method of manufacturing a semiconductor device, the method comprising:

depositing a low-k dielectric layer;

forming a trench in the low-k dielectric layer;

forming a barrier layer in the trench;

filling copper on the barrier layer to form a copper layer;

planarizing the copper layer;

applying plasma to the planarized copper layer;

forming an aluminum nitride (AlN) layer on the planarized copper layer by using a plasma-enhanced atomic layer deposition (PEALD) method; and

forming a silicon nitride (SiN) layer on the AlN layer in-situ in a reactor in which the AlN layer has been formed,

wherein a sum of a thickness of the AlN layer and a thickness of the SiN layer ranges from about 50 Å

to about 100Å

, and

wherein the forming the AlN layer and the forming of the SiN layer are performed at a temperature ranging from about 250°

C. to about 350°

C.

16. A method of manufacturing a semiconductor device, the method comprising:

forming a first dielectric layer;

forming a first metal layer in the first dielectric layer; and

forming a capping layer with a thickness less than 100 Å

on the first dielectric layer and the first metal layer, wherein the forming of the capping layer comprises;

forming an aluminum nitride layer; and

forming a silicon nitride layer on the aluminum nitride layer, and wherein the aluminum nitride layer is located between the first metal layer and the silicon nitride layer; and

forming a second dielectric layer on the said capping layer;

forming a second metal layer in the said second dielectric layer; and

forming a second capping layer with a thickness less than 100 Å

on the second dielectric layer and the second first metal layer, wherein the forming of the second capping layer comprises;

forming an second aluminum nitride layer;

forming a second silicon nitride layer on the second aluminum nitride layer; and

wherein a part of the second metal layer contacts the first metal layer and the side wall of the said first capping, layer.