Stacked substrate inductor

• US 10,249,580 B2
• Filed: 06/22/2016
• Issued: 04/02/2019
• Est. Priority Date: 06/22/2016
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kim, Daeik Daniel, Yun, Changhan Hobie, Berdy, David Francis, Zuo, Chengjie, Velez, Mario Francisco, Kim, Jonghae
• Primary Examiner(s): Lee, Calvin
• Application Number:
  US15/190,158
• Publication Number:
  US 20170373025A1
• Time in Patent Office: 1,014 Days
• Field of Search: 438 57, 257422, 257531
• CPC Class Codes: H01F 41/041 Printed circuit coils apparatus or processes for manufacturing printed circuits in general H05K3/00
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/30107 Inductance

Abstract

In conventional device packages, separate standalone inductors are provided and mounted on an interposer substrate along with a die. Separate inductors reduce integration density, decrease flexibility, increase footprint, and generally increase costs. To address such disadvantages, it is proposed to provide a part of an inductor in a substrate below a die. The proposed stacked substrate inductor may include a first inductor in a first substrate, a second inductor in a second a second substrate stacked on the first substrate, and an inductor interconnect coupling the first and second inductors. The core regions of the first and second inductors may overlap with each other at least partially. The proposed stacked substrate inductor may enhance integration density, increase flexibility, decrease footprint, and/or reduce costs.

Claims

1. A stacked substrate inductor, comprising:

a first substrate;

a second substrate stacked on the first substrate such that an upper side of the first substrate is in direct contact with a lower side of the second substrate;

a first inductor within and in direct contact with the first substrate, the first inductor including a first core region;

a second inductor within and in direct contact with the second substrate, the second inductor including a second core region;

an inductor interconnect within and in direct contact with the second substrate, the inductor interconnect configured to electrically couple the first inductor with the second inductor,

wherein at least a portion of the first core region overlaps with at least a portion of the second core region,

wherein the second inductor comprises a plurality of second substrate inductance loops, and

wherein the second substrate encapsulates the second inductor such that each of the plurality of second substrate inductance loops is in direct contact with the second substrate.

2. The stacked substrate inductor of claim 1,

wherein the first substrate is an interposer substrate, and

wherein the second substrate is a die substrate.

3. The stacked substrate inductor of claim 1, wherein the first inductor and the second inductor are both looped substantially in a rectangle.

4. The stacked substrate inductor of claim 1, wherein the first inductor and the second inductor are both looped substantially in a spiral.

5. The stacked substrate inductor of claim 1, further comprising a magnetic core in the first and second core regions.

6. The stacked substrate inductor of claim 1, further comprising a third inductor within the second substrate,

wherein a core region of the third inductor is a third core region, and

wherein at least a portion of the third core region overlaps with at least a portion of the first core region.

7. The stacked substrate inductor of claim 6,

wherein each of the second and third inductors is electrically in series with the first inductor, and

wherein the second and third inductors are electrically in parallel with each other.

8. The stacked substrate inductor of claim 6, wherein there is no overlap between the second and third core regions.

9. The stacked substrate inductor of claim 1,

wherein the first inductor comprises one or more first substrate inductance loops, or

wherein the second inductor comprises one or more second substrate inductance loops, or both.

10. The stacked substrate inductor of claim 9,

wherein when the first inductor comprises a plurality of first substrate inductance loops, each pair of adjacent first substrate inductance loops are configured to be electrically coupled by a corresponding first substrate loop interconnect, and

wherein when the second inductor comprises a plurality of second substrate inductance loops, each pair of adjacent second substrate inductance loops are configured to be electrically coupled by a corresponding second substrate loop interconnect.

11. The stacked substrate inductor of claim 9,

wherein when the first inductor comprises a plurality of first substrate inductance loops, none of the plurality of first substrate inductance loops is circumscribed by another of the plurality of first substrate inductance loops at a same level, or

wherein when the second inductor comprises a plurality of second substrate inductance loops, none of the plurality of second substrate inductance loops is circumscribed by another of the plurality of second substrate inductance loops at a same level, or

both.

12. A device package, comprising:

a first substrate;

a second substrate stacked on the first substrate such that an upper side of the first substrate is in direct contact with a lower side of the second substrate;

a first inductor within and in direct contact with the first substrate, the first inductor including a first core region;

a die and a second inductor within and in direct contact with the second substrate, the second inductor including a second core region;

an inductor interconnect within and in direct contact with the second substrate, the inductor interconnect configured to electrically couple the first inductor with the second inductor,

wherein at least a portion of the first core region overlaps with at least a portion of the second core region,

wherein the second inductor comprises a plurality of second substrate inductance loops, and

wherein the second substrate encapsulates the second inductor and the die such that each of the plurality of second substrate inductance loops is in direct contact with the second substrate and the die is in direct contact with the second substrate.

13. The device package of claim 12,

wherein when the first inductor comprises a plurality of first substrate inductance loops, each pair of adjacent first substrate inductance loops configured to be electrically coupled by a corresponding first substrate loop interconnect, and

wherein when the second inductor comprises a plurality of second substrate inductance loops, each pair of adjacent second substrate inductance loops configured to be electrically coupled by a corresponding second substrate loop interconnect.

14. The device package of claim 12,

wherein when the first inductor comprises a plurality of first substrate inductance loops, none of the plurality of first substrate inductance loops is circumscribed by another of the plurality of first substrate inductance loops at a same level, or

wherein when the second inductor comprises a plurality of second substrate inductance loops, none of the plurality of second substrate inductance loops is circumscribed by another of the plurality of second substrate inductance loops at a same level, or

both.

15. The device package of claim 12,

wherein the first inductor is shaped to be adjacent to a periphery of first and second sides of the die, or

wherein the second inductor is shaped to be adjacent to the periphery of first and second sides of the die, or

both.

16. The device package of claim 12,

wherein the first substrate is an interposer substrate, and

wherein the second substrate is a die substrate.

17. The device package of claim 12, wherein a height of the second inductor is less than or substantially equal to a height of the die.

18. The device package of claim 12, wherein the first inductor and the second inductor are both looped substantially in a rectangle.

19. The device package of claim 12, wherein the first inductor and the second inductor are both looped substantially in a spiral.

20. The device package of claim 12, further comprising a magnetic core in the first and second core regions.

21. The device package of claim 12, further comprising a third inductor within the second substrate,

wherein a core region of the third inductor is a third core region, and

wherein at least a portion of the third core region overlaps with at least a portion of the first core region.

22. The device package of claim 21,

wherein the first inductor is adjacent to a periphery of first and second sides of the die,

wherein the second inductor is adjacent to the periphery of the first side of the die, and

wherein the third inductor is adjacent to the periphery of the second side of the die.

23. The device package of claim 21,

wherein each of the second and third inductors is electrically in series with the first inductor, and

wherein the second and third inductors are electrically in parallel with each other.

24. The device package of claim 21, wherein there is no overlap between the second and third core regions.

25. A stacked substrate inductor, comprising:

a first substrate;

a second substrate stacked on the first substrate such that an upper side of the first substrate is in direct contact with a lower side of the second substrate;

means for providing a first inductance within and in direct contact with the first substrate, the means for providing the first inductance including a first core region;

means for providing a second inductance within and in direct contact with the second substrate, the means for providing the second inductance including a second core region;

means for providing an interconnect for electrically coupling the means for providing the first inductance with the means for providing the second inductance,

wherein the means for providing the interconnect is within and in direct contact with the second substrate,

wherein at least a portion of the first core region overlaps with at least a portion of the second core region,

wherein the means for providing the second inductance comprises means for providing a plurality of second loop inductances, and

wherein the second substrate encapsulates the means for providing the second inductance such that each of the plurality of second loop inductances is in direct contact with the second substrate.

26. The stacked substrate inductor of claim 25, further comprising a magnetic core in the first and second core regions.

27. The stacked substrate inductor of claim 25, further comprising means for providing a third inductance within the second substrate;

wherein a core region of the means for providing the third inductance is a third core region,

wherein at least a portion of the third core region overlaps with at least a portion of the second core region, and

wherein there is no overlap between the second and third core regions.

28. The stacked substrate inductor of claim 27,

wherein the means for providing the second inductance is electrically in series with the means for providing the first inductance,

wherein the means for providing the third inductance is electrically in series with the means for providing the first inductance, and

wherein the means for providing the second inductance is electrically in parallel with the means for providing the third inductance.