Stacked nanosheet field effect transistor device with substrate isolation

• US 10,249,709 B2
• Filed: 10/20/2017
• Issued: 04/02/2019
• Est. Priority Date: 02/02/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Li, Juntao, Wang, Geng, Zhang, Qintao
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US15/789,325
• Publication Number:
  US 20180219064A1
• Time in Patent Office: 529 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Nanosheet FET devices having substrate isolation layers are provided, as well as methods for fabricating nanosheet FET devices with substrate isolation layers. For example, a semiconductor device includes a nanosheet stack structure formed on a substrate, which includes a rare earth oxide (REO) layer formed on the substrate, and a semiconductor channel layer disposed adjacent to the REO layer. A metal gate structure is formed over the nanosheet stack structure, and a gate insulating spacer is disposed on sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer. Source/drain regions are formed in contact with the exposed end portions of the semiconductor channel layer. A portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the substrate.

Claims

1. A semiconductor device, comprising:

a nanosheet stack structure formed on a semiconductor substrate, wherein the nanosheet stack structure comprises a rare earth oxide (REO) layer formed on the semiconductor substrate, and a semiconductor channel layer disposed adjacent to the REO layer;

a metal gate structure formed over the nanosheet stack structure;

a gate insulating spacer disposed on vertical sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer; and

a first source/drain region and a second source/drain region formed in contact with a respective one of the end portions of the semiconductor channel layer exposed through the gate insulating spacer;

wherein a portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the semiconductor substrate;

wherein the first and second source/drain regions comprise an epitaxial semiconductor material that is epitaxially grown on the end portions of the semiconductor channel layer, and wherein the first and second source/drain regions are formed in contact with portions of the REO layer which extend past the gate insulating spacer such that the REO layer isolates the first and second source/drain regions from the semiconductor substrate.

2. The semiconductor device of claim 1, wherein the REO layer comprises an epitaxial REO material that is epitaxially grown on the semiconductor substrate, and wherein the semiconductor channel layer comprises an epitaxial semiconductor material that is epitaxially grown.

3. The semiconductor device of claim 1, wherein an upper surface of the REO layer which is adjacent to the semiconductor channel layer comprises a non-planar profile.

4. The semiconductor device of claim 1, wherein an upper surface of the REO layer which is adjacent to the semiconductor channel layer comprises a planar profile.

5. The semiconductor device of claim 1, wherein the metal gate structure comprises:

a conformal gate dielectric layer formed on surfaces of the semiconductor channel layer; and

one or more layers of metallic material formed on the conformal gate dielectric layer and filling a gate region surrounded by the gate insulating spacer;

wherein the one or more layers of metallic material comprises at least one of a work function metal layer and a gate electrode layer.

6. A semiconductor device, comprising:

a nanosheet stack structure formed on a semiconductor substrate, wherein the nanosheet stack structure comprises a rare earth oxide (REO) layer formed on the semiconductor substrate, and a semiconductor channel layer disposed adjacent to the REO layer;

a metal gate structure formed over the nanosheet stack structure;

a gate insulating spacer disposed on vertical sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer; and

a first source/drain region and a second source/drain region formed in contact with a respective one of the end portions of the semiconductor channel layer exposed through the gate insulating spacer;

wherein a portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the semiconductor substrate;

wherein at least one of the first source/drain region and the second source/drain region is formed in contact with a portion of the REO layer which extends past the gate insulating spacer; and

wherein said at least one of the first source/drain region and the second source/drain region, which is formed in contact with the portion of the REO layer that extends past the gate insulating spacer, is isolated from the semiconductor substrate by the REO layer.

7. The semiconductor device of claim 6, wherein the REO layer comprises an epitaxial REO material that is epitaxially grown on the semiconductor substrate, and wherein the semiconductor channel layer comprises an epitaxial semiconductor material that is epitaxially grown.

8. The semiconductor device of claim 6, wherein the first and second source/drain regions comprise an epitaxial semiconductor material that is epitaxially grown on the end portions of the semiconductor channel layer.

9. The semiconductor device of claim 6, further comprising an isolation layer formed in the surface of the semiconductor substrate adjacent to at least one side of the nanosheet stack structure, wherein at least one of the first source/drain region and the second source/drain region is disposed on the isolation layer and isolated from the semiconductor substrate by the isolation layer.

10. The semiconductor device of claim 6, wherein an upper surface of the REO layer which is adjacent to the semiconductor channel layer comprises a non-planar profile.

11. The semiconductor device of claim 6, wherein an upper surface of the REO layer which is adjacent to the semiconductor channel layer comprises a planar profile.

12. The semiconductor device of claim 6, wherein the metal gate structure comprises:

a conformal gate dielectric layer formed on surfaces of the semiconductor channel layer; and

one or more layers of metallic material formed on the conformal gate dielectric layer and filling a gate region surrounded by the gate insulating spacer;

wherein the one or more layers of metallic material comprises at least one of a work function metal layer and a gate electrode layer.