Semiconductor device including a gate trench and a source trench

• US 10,249,721 B2
• Filed: 04/04/2013
• Issued: 04/02/2019
• Est. Priority Date: 04/04/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Blank, Oliver
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): Jefferson, Quovaunda V
• Application Number:
  US13/856,689
• Publication Number:
  US 20140299932A1
• Time in Patent Office: 2,189 Days
• Field of Search: 257213-413, 257900, 257902-903, 257E2119-E2121, 257E21394-E21458, 257E21615-E21694, 257E21431-E21435, 257E21619-E2162, 257E29, 257E29255-E29313, 257E29315-E29316, 257E21409-E21449, 257E29027-E29028, 257E29066-E29067, 257E29194-E29202, 257E21382-E21385, 257E21608-E21613, 438135, 438142, 438151, 438197, 438199, 438201, 438207, 438216
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a source trench extending into a semiconductor body from a first surface of the semiconductor body. A source trench dielectric and a source trench electrode are in the source trench. A gate trench dielectric and a gate trench electrode are in a gate trench extending into the semiconductor body from the first surface. A body region of a first conductivity type is between the gate and source trenches. A source region of a second conductivity type different from the first conductivity type is between the gate and source trenches. An interconnection electrically couples the body region and the source trench electrode. The interconnection adjoins a lateral face of the source trench electrode and the body region. A source contact is on the source trench electrode at the first surface.

Claims

1. A semiconductor device, comprising:

a source trench extending into a semiconductor body from a first surface of the semiconductor body;

a source trench dielectric and a source trench electrode in the source trench;

a gate trench dielectric and a gate trench electrode in a gate trench extending into the semiconductor body from the first surface;

a body region of a first conductivity type between the gate and source trenches;

a source region of a second conductivity type different from the first conductivity type between the gate and source trenches;

an interconnection electrically coupling the body region and the source trench electrode,

wherein the interconnection laterally extends through the source trench dielectric in a direction that is parallel to the first surface and adjoins a lateral face of the source trench electrode and of the body region, the lateral face of the source trench electrode and of the body region being perpendicular to the first surface,

and wherein an interface between the source trench dielectric and the semiconductor body at a sidewall of the source trench is step shaped at a transition between lower and upper parts of the source trench dielectric;

wherein the step shaped interface between the source trench dielectric and the semiconductor body directly contacts the source trench dielectric and the semiconductor body, and

a source contact on the source trench electrode at the first surface.

2. The semiconductor device of claim 1, wherein the source contact overlaps the source region by less than 100 nm along a lateral direction extending between the gate and source trenches parallel to the first surface.

3. The semiconductor device of claim 1, wherein a bottom side of the body region overlaps a top side of the source trench dielectric of the lower part of the source trench along a lateral direction extending between the gate and source trenches parallel to the first surface.

4. The semiconductor device of claim 1, wherein the source contact on the source trench electrode is laterally spaced from the source region.

5. The semiconductor device of claim 1, further comprising a body contact region of the first conductivity type between the body region and the interconnection wherein a doping of the body contact region is greater than 10¹⁹ cm−

3.

6. The semiconductor device of claim 1, wherein the interconnection includes at least one of doped polysilicon and metal.

7. The semiconductor device of claim 1, wherein a thickness of the gate trench dielectric at a bottom side of the gate trench electrode is greater than a thickness of the gate trench dielectric at a sidewall of the gate trench.

8. The semiconductor device of claim 1, wherein the gate trench is self-aligned with respect to a first source trench and a second source trench.