Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors

• US 10,249,762 B2
• Filed: 03/28/2018
• Issued: 04/02/2019
• Est. Priority Date: 08/26/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bergendahl, Marc A., Cheng, Kangguo, Miller, Eric R., Sporre, John R., Teehan, Sean
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US15/938,367
• Publication Number:
  US 20180219101A1
• Time in Patent Office: 370 Days
• Field of Search: 257213, 257344, 257347, 257365, 257401, 257E29004, 257E29022, 257E29117, 257E29128, 257E29137, 257E29286, 257E29296, 257E21409, 257E21415, 257E21421, 257E21431, 438157, 438282, 438284, 438300, 438305, 438686
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78681 : having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H05K 999/99 : dummy group

Abstract

A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.

Claims

1. A method for forming a semiconductor structure, the method comprising:

forming a structure comprising at least an alternating stack of semiconductor layers and metal gate material layers formed on a substrate, a metal gate formed on and in contact with a top layer of the alternating stack, a source region and a drain region in contact with the alternating stack, and dielectric layers formed on and in contact with a top surface of the source and drain regions, respectively;

removing a portion of the semiconductor layers and metal gate material layers, wherein the removing forms trenches exposing at least sidewalls of the source and drain regions;

forming a first plurality of interconnects between and in contact with the semiconductor layers and the source region; and

forming a second plurality of interconnects between and in contact with the semiconductor layers and the drain region.

2. The method of claim 1, further comprising:

prior to removing the portion of the semiconductor layers and metal gate material layers, etching spacers surrounding the source region, the drain region, and the dielectric layers, wherein the etching forms trenches between the metal gate and the dielectric layers and above the portion of the semiconductor layers and metal gate material layers.

3. The method of claim 2, further comprising:

after the first and second plurality of interconnects have been formed, depositing a spacer material within the trenches.

4. The method of claim 1, wherein forming the first and second plurality of interconnects forms air pockets between the metal gate material layers and the source region, and between the metal gate material layers and the drain region.

5. The method of claim 1, wherein forming the structure comprises:

forming an alternating vertical stack of the semiconductor layers and sacrificial semiconductor layers;

forming at least one disposable gate on the alternating vertical stack; and

forming a spacer around the disposable gate and a portion of the alternating vertical stack underlying the disposable gate.

6. The method of claim 5, further comprising:

forming a cap layer on and in contact with a top portion of the alternating stack of semiconductor layers.

7. The method of claim 5, wherein forming the structure comprises:

epitaxially growing each semiconductor layer and each sacrificial semiconductor layer in the alternating stack of semiconductor layers and sacrificial semiconductor layers.

8. The method of claim 7, wherein the forming further comprises:

patterning the alternating stack of semiconductor layers and sacrificial semiconductor layers.

9. The method of claim 5, wherein forming the structure further comprises:

removing the disposable gate, the removing forming a trench exposing the portion of the alternating vertical stack; and

removing the sacrificial semiconductor layers.

10. The method of claim 9, wherein forming the structure further comprises

depositing metal gate material within the trench, wherein the depositing forms the metal gate and the metal gate material layers.

11. The method of claim 5, wherein forming the structure further comprises:

removing a first portion of the alternating vertical stack in a first area corresponding to the source region;

removing a second portion of the alternating vertical stack in a second area corresponding to the drain region; and

epitaxially growing the source region and the drain region within the first and second areas, respectively, wherein the source and drain regions are grown in contact with the portion of the alternating vertical stack underlying the disposable gate.

12. The method of claim 11, further comprising:

depositing an inter-layer dielectric material on and in contact with the source region and the drain region.

13. The method of claim 1, further comprising:

forming a cap layer on and in contact with the metal gate.

14. A method for forming a semiconductor structure, the method comprising:

forming an alternating stack of semiconductor layers and metal gate material layers on a substrate;

forming a metal gate on and in contact with a top layer of the alternating stack;

removing a portion of the semiconductor layers and metal gate material layers, wherein the removing forms at least one trench; and

forming a plurality of interconnects within the at least one trench, wherein each interconnect in plurality of interconnects contacts a semiconductor layer of the alternating stack, the formation of the plurality of interconnects forms air pockets between pairs of interconnects in the plurality of interconnects.

15. The method of claim 14, further comprising:

after the plurality of interconnects have been formed, depositing a spacer material within the first and second trenches.

16. The method of claim 14, wherein forming alternating stack of semiconductor layers and metal gate material layers comprises:

forming an alternating vertical stack of the semiconductor layers and sacrificial semiconductor layers.

17. The method of claim 16, further comprising:

patterning the alternating vertical stack of semiconductor layers and sacrificial semiconductor layers.

18. The method of claim 16, further comprising:

removing the sacrificial semiconductor layers, the removing forming voids between the semiconductor layers; and

depositing metal gate material within the voids, wherein the depositing forms the metal gate material layers.

19. The method of claim 14, wherein forming the metal gate comprises:

forming an alternating vertical stack of the semiconductor layers and sacrificial semiconductor layers;

forming at least one disposable gate on the alternating vertical stack;

forming a spacer around the disposable gate and a portion of the alternating vertical stack underlying the disposable gate;

after forming the spacer, removing the disposable gate, the removing forming a trench exposing the portion of the alternating vertical stack;

removing the sacrificial semiconductor layers; and

depositing metal gate material within the trench, wherein the depositing forms the metal gate and the metal gate material layers.

20. A method for forming a semiconductor structure, the method comprising:

forming a structure comprising at least

a plurality of alternating stacks each comprising semiconductor layers and metal gate material layers formed on a substrate, and a plurality of doped regions each in contact with at least one alternating stack of the plurality of stacks;

removing a portion of each alternating stack of the plurality of stacks in contact with at least one doped region of the plurality of doped regions, the removing forming a plurality of trenches exposing a sidewall of the at least one doped region; and

epitaxially growing a plurality of interconnects within the trenches, wherein each interconnect of the plurality of interconnects is between and in contact with one of the semiconductor layers and one doped region of the plurality of doped regions.