Cascode amplifier bias circuits

• US 10,250,199 B2
• Filed: 09/16/2016
• Issued: 04/02/2019
• Est. Priority Date: 09/16/2016
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Inventors: Klaren, Jonathan, Wagh, Poojan, Kovac, David, Shapiro, Eric S., Calanca, Neil, Nobbe, Dan William, Murphy, Christopher, Englekirk, Robert Mark, Ayranci, Emre, Bargroff, Keith, Ranta, Tero Tapio
• Primary Examiner(s): Nguyen, Patricia T
• Application Number:
  US15/268,229
• Publication Number:
  US 20180083578A1
• Time in Patent Office: 928 Days
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/105 A non-specified detector of the power of a signal being used in an amplifying circuit
• CPC Class Codes: H03F 2200/165 A filter circuit coupled to the input of an amplifier
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/21 Bias resistors are added at the input of an amplifier
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/225 the input circuit of an amplifying stage comprising an LC-network
• CPC Class Codes: H03F 2200/243 A series resonance being added in series in the input circuit, e.g. base, gate, of an amplifier stage
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/297 the loading circuit of an amplifying stage comprising a capacitor
• CPC Class Codes: H03F 2200/301 the loading circuit of an amplifying stage comprising a coil
• CPC Class Codes: H03F 2200/306 the loading circuit of an amplifying stage being a parallel resonance circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/391 the output circuit of an amplifying stage comprising an LC-network
• CPC Class Codes: H03F 2200/399 A parallel resonance being added in shunt in the output circuit, e.g. base, gate, of an amplifier stage
• CPC Class Codes: H03F 2200/42 the input to the amplifier being made by capacitive coupling means
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/48 : the output of the amplifier being coupled out by a capacitor
• CPC Class Codes: H03F 2200/489 : A coil being added in the source circuit of a common source stage, e.g. as degeneration means
• CPC Class Codes: H03F 2200/492 : A coil being added in the source circuit of a transistor amplifier stage as degenerating element
• CPC Class Codes: H03F 2200/498 : A resistor being added in the source circuit of a transistor amplifier stage as degenerating element
• CPC Class Codes: H03F 2200/555 : A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 2200/61 : the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 2200/78 : A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 3/193 : with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/213 : in integrated circuits
• CPC Class Codes: H03F 3/245 : with semiconductor devices only

Abstract

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Claims

1. An amplifier circuit including:

(a) a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;

(b) a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit;

(c) a closed loop bias control circuit, having at least one input coupled to the cascode reference circuit and an output coupled to the gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit, responsive to variations in voltage and/or current in the cascode reference circuit to output an adjustment gate bias voltage applied to the respective gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit that forces the mirror current in the cascode reference circuit to be approximately equal to a selected current value; and

(d) a respective decoupling network coupled between corresponding gates of each of the bottom two FET stages of the cascode amplifier, wherein at least one decoupling network includes a programmable resistance element for varying bias levels to the coupled gates.

3. The invention of claim 1, wherein the corresponding drain voltages of the bottom FET stage of the cascode amplifier and the cascode reference circuit are approximately the same.

4. The invention of claim 1, wherein the cascode reference circuit is a split cascode reference circuit.

5. The invention of claim 1, further including an input impedance matching network coupled to the input of the bottom FET stage and configured to be coupled to the RF input signal to be amplified.

6. The invention of claim 1, further including an output impedance matching network coupled to the output.

8. The invention of claim 1, wherein the input to the bottom FET stage is coupled to the gate of the bottom FET stage.

9. The invention of claim 1, wherein the input to the bottom FET stage is coupled to the source of the bottom FET stage.

10. The invention of claim 1, further including a source voltage, coupled to the cascode amplifier and the cascode reference circuit, having a range of about 0.4V to about 4.5V.

11. The invention of claim 1, further including a bias voltage, coupled to the gates of the cascode amplifier, having a range of about 0.4V to about 4.5V.

12. The invention of claim 1, wherein the RF input signal includes frequencies from and above about 100 MHz.

13. The invention of claim 1, wherein the FETs in the cascode amplifier and in the cascode reference circuit have gate lengths less than about 1 μ

m.

2. An amplifier circuit including:

(a) a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;

(b) a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit; and

(c) a current source, coupled to the drain of the top FET stage of the cascode reference circuit and to the respective gates of the bottom FET stages of the cascode reference circuit and the cascode amplifier; and

(d) a respective decoupling network coupled between corresponding gates of each of the bottom two FET stages of the cascode amplifier, wherein at least one decoupling network includes a programmable resistance element for varying bias levels to the coupled gates;

wherein the respective gates of the bottom FET stages of the cascode reference circuit and the cascode amplifier are responsive to variations in voltage in the cascode reference circuit such that the mirror current in the cascode reference circuit is forced to be approximately equal to a selected current value.

7. An amplifier circuit including:

(a) a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;

(b) a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit

(c) a closed loop bias control circuit, having at least one input coupled to the cascode reference circuit and an output coupled to the gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit, responsive to variations in voltage and/or current in the cascode reference circuit to output an adjustment gate bias voltage applied to the respective gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit that forces the mirror current in the cascode reference circuit to be approximately equal to a selected current value;

(d) a degeneration inductor coupled between the source of the bottom FET stage of the cascode amplifier and RF ground, the degeneration inductor having a resistance Rdeg; and

(e) a compensation resistor coupled between the source of the bottom FET stage of the cascode reference circuit and RF ground, the compensation resistor having a resistance Rcomp such that the voltage at the source of the bottom FET stage of the cascode reference circuit closely approximates the voltage at the source of the bottom FET stage of the cascode amplifier.

14. The invention of claim 7, wherein the corresponding drain voltages of the bottom FET stage of the cascode amplifier and the cascode reference circuit are approximately the same.

15. The invention of claim 7, wherein the cascode reference circuit is a split cascode reference circuit.

16. The invention of claim 7, further including an input impedance matching network coupled to the input of the bottom FET stage and configured to be coupled to the RF input signal to be amplified.

17. The invention of claim 7, further including an output impedance matching network coupled to the output.

18. The invention of claim 7, further including a respective decoupling network coupled between corresponding gates of each of the bottom two FET stages of the cascode amplifier.

19. The invention of claim 18, wherein at least one decoupling network includes a programmable resistance element for varying bias levels to the coupled gates.

20. The invention of claim 7, wherein the input to the bottom FET stage is coupled to the gate of the bottom FET stage.

21. The invention of claim 7, wherein the input to the bottom FET stage is coupled to the source of the bottom FET stage.

22. The invention of claim 7, further including a source voltage, coupled to the cascode amplifier and the cascode reference circuit, having a range of about 0.4V to about 4.5V.

23. The invention of claim 7, further including a bias voltage, coupled to the gates of the cascode amplifier, having a range of about 0.4V to about 4.5V.

24. The invention of claim 7, wherein the RF input signal includes frequencies from and above about 100 MHz.

25. The invention of claim 7, wherein the FETs in the cascode amplifier and in the cascode reference circuit have gate lengths less than about 1 μ

m.