Semiconductor device and circuit arrangement using the same

• US 10,250,255 B2
• Filed: 04/06/2016
• Issued: 04/02/2019
• Est. Priority Date: 04/16/2015
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Yanagigawa, Hiroshi
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US15/091,827
• Publication Number:
  US 20160308529A1
• Time in Patent Office: 1,091 Days
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H03K 17/06 Modifications for ensuring a fully conducting state
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration

Abstract

A semiconductor device and a circuit arrangement are provided so as to reduce an on resistance. A first power MOS transistor and a second power MOS transistor are formed on the same semiconductor substrate. A first power MOS transistor formed in a first element formation region has a columnless structure including no columns. The second power MOS transistor formed in a second element formation region has an SJ structure including columns.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer of the first conductivity type in contact with a surface of the semiconductor substrate;

first and second regions determined with a certain distance in the epitaxial layer;

a first switching element that is formed in the first region and is electrically coupled to the semiconductor substrate;

a second switching element that is formed in the second region and is electrically coupled to the semiconductor substrate so as to be coupled in series to the first switching element,

the first switching element including;

a first electrode formed in a first trench via a first insulating film, the first trench being formed over the epitaxial layer;

a first-impurity-region first part of the second conductivity type in the epitaxial layer, the first-impurity-region first part being formed with a first thickness in contact with the first insulating film at a smaller depth than a bottom of the first trench; and

a second-impurity-region first part of the first conductivity type in the epitaxial layer, the second-impurity-region first part being formed in contact with the first-impurity-region first part at a smaller depth than the first-impurity-region first part,

the second switching element including;

a second electrode formed in a second trench via a second insulating film, the second trench being formed over the epitaxial layer;

a first-impurity-region second part of the second conductivity type in the epitaxial layer, the first-impurity-region second part being formed with a second thickness in contact with the second insulating film at a smaller depth than a bottom of the second trench;

a second-impurity-region second part of the first conductivity type in the epitaxial layer, the second-impurity-region second part being formed in contact with the first-impurity-region second part at a smaller depth than the first-impurity-region second part; and

columns of the second conductivity type, the columns being extended from the first-impurity-region second part toward the semiconductor substrate and away from both the second insulating film and the second electrode.

2. The semiconductor device according to claim 1, wherein the first thickness of the first-impurity-region first part is smaller than the second thickness of the first-impurity-region second part.

3. A circuit arrangement using the semiconductor device according to claim 2 as a switch,

the circuit arrangement comprising:

a battery having a cathode and an anode, the cathode being electrically coupled to the second-impurity-region first part, the anode being electrically coupled to the second-impurity-region second part; and

a load electrically coupled between the anode of the battery and the switch.

4. The semiconductor device according to claim 1, wherein the second trench is formed in one direction, and the columns are spaced at certain intervals in the one direction.

5. A circuit arrangement using the semiconductor device according to claim 4 as a switch,

the circuit arrangement comprising:

a battery having a cathode and an anode, the cathode being electrically coupled to the second-impurity-region first part, the anode being electrically coupled to the second-impurity-region second part; and

a load electrically coupled between the anode of the battery and the switch.

6. A circuit arrangement using the semiconductor device according to claim 1 as a switch,

the circuit arrangement comprising:

a battery having a cathode and an anode, the cathode being electrically coupled to the second-impurity-region first part, the anode being electrically coupled to the second-impurity-region second part; and

a load electrically coupled between the anode of the battery and the switch.

7. The semiconductor device according to claim 1, wherein in a direction perpendicular to the direction in which the columns are extended, the columns are within the second switching element and spaced apart from each of the second trench, the second electrode and the second insulating film.

8. The semiconductor device according to claim 1, wherein a withstand voltage of the second switching element is greater than a withstand voltage of the first switching element.

9. The semiconductor device according to claim 8, wherein the withstand voltage of the second switching element is greater than twice the withstand voltage of the first switching element.