Digital circuits having improved transistors, and methods therefor

• US 10,250,257 B2
• Filed: 04/27/2018
• Issued: 04/02/2019
• Est. Priority Date: 02/18/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Thompson, Scott E., Clark, Lawrence T.
• Primary Examiner(s): Tran, Anh Q
• Application Number:
  US15/964,359
• Publication Number:
  US 20180248548A1
• Time in Patent Office: 340 Days
• Field of Search: None
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

Claims

1. A logic circuit, comprising:

first and second transistors of different conductivity types having controllable current paths coupled between an input node and an output node, the first and second transistors arranged in parallel to one another between the input node and the output node, the first and second transistors receive complementary signals at their gates, respectively;

wherein each of the first and second transistors has a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed fully over a relatively highly doped screening layer formed fully over and in contact with a doped body region.