PVT compensated resistive biasing architecture for a capacitive sensor
First Claim
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1. A circuit comprising:
- a first plurality of serially-coupled transistors coupled between a first node and a second node;
a second plurality of serially-coupled transistors coupled between the first node and the second node; and
a voltage divider circuit in communication with the second node, the voltage divider circuit comprising a plurality of outputs, a first group of outputs of the plurality of outputs coupled to corresponding control nodes associated with the first plurality of serially-coupled transistors, and a second group of outputs of the plurality of outputs different from the first group of outputs coupled to corresponding control nodes associated with the second plurality of serially-coupled transistors, the control nodes comprising at least one of bulk nodes or gate nodes.
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Abstract
A circuit for biasing a MEMS microphone includes a first group of serially-coupled transistors coupled between a first node and a second node, a second group of serially-coupled transistors coupled between the first node and the second node, and a voltage divider circuit coupled to the second node having a number of outputs, a first group of outputs being coupled to corresponding control nodes associated with the first group of serially-coupled transistors, and a second group of outputs different from the first group of outputs coupled to corresponding control nodes associated with the second group of serially-coupled transistors, the control nodes being either bulk nodes or gate nodes.
9 Citations
24 Claims
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1. A circuit comprising:
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a first plurality of serially-coupled transistors coupled between a first node and a second node; a second plurality of serially-coupled transistors coupled between the first node and the second node; and a voltage divider circuit in communication with the second node, the voltage divider circuit comprising a plurality of outputs, a first group of outputs of the plurality of outputs coupled to corresponding control nodes associated with the first plurality of serially-coupled transistors, and a second group of outputs of the plurality of outputs different from the first group of outputs coupled to corresponding control nodes associated with the second plurality of serially-coupled transistors, the control nodes comprising at least one of bulk nodes or gate nodes. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A circuit comprising:
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a first plurality of serially-coupled transistors coupled between a first node and a second node; a second plurality of serially-coupled transistors coupled between the first node and the second node; a first voltage divider circuit in communication with the second node, the first voltage divider circuit comprising a plurality of outputs, a first group of outputs of the plurality of outputs coupled to corresponding bulk nodes associated with the first plurality of serially-coupled transistors, and a second group of outputs of the plurality of outputs different from the first group of outputs coupled to corresponding bulk nodes associated with the second plurality of serially-coupled transistors; and a second voltage divider circuit in communication with the second node, the second voltage divider circuit comprising a plurality of outputs, a first group of outputs of the plurality of outputs coupled to corresponding gate nodes associated with the first plurality of serially-coupled transistors, and a second group of outputs of the plurality of outputs different from the first group of outputs coupled to corresponding gate nodes associated with the second plurality of serially-coupled transistors. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method of operating a device comprising a first plurality of serially-coupled transistors between a first node and a second node, a second plurality of serially-coupled transistors between the first node and the second node, a third plurality of serially-coupled transistors coupled between the first node and a third node, and a fourth plurality of serially-coupled transistors coupled between the first node and the third node, the method comprising:
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driving control nodes associated with the first plurality of serially-coupled transistors with a first set of voltages associated with the first and second nodes; driving control nodes associated with the second plurality of serially-coupled transistors with a second set of voltages associated with the first and second nodes, driving control nodes associated with the third plurality of serially-coupled transistors with a third set of voltages associated with the first and third nodes; and driving control nodes associated with the fourth plurality of serially-coupled transistors with a fourth set of voltages associated with the first and third nodes, wherein the control nodes comprise at least one of bulk nodes or gate nodes. - View Dependent Claims (16, 17, 18, 19)
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20. A method of operating a device comprising a first plurality of serially-coupled transistors between a first node and a second node, and a second plurality of serially-coupled transistors between the first node and the second node, the method comprising:
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driving control nodes associated with the first plurality of serially-coupled transistors with a first set of voltages associated with the first and second nodes; driving control nodes associated with the second plurality of serially-coupled transistors with a second set of voltages associated with the first and second nodes, wherein the control nodes comprise at least one of bulk nodes or gate nodes; and biasing a MEMS microphone via the second node. - View Dependent Claims (21, 22, 23, 24)
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Specification