PVT compensated resistive biasing architecture for a capacitive sensor

• US 10,250,999 B1
• Filed: 09/18/2017
• Issued: 04/02/2019
• Est. Priority Date: 09/18/2017
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Polo, Francesco, Gaggl, Richard, Muehlbacher, Benno, Valli, Luca
• Primary Examiner(s): Jerez Lora, William A
• Application Number:
  US15/706,973
• Publication Number:
  US 20190090066A1
• Time in Patent Office: 561 Days
• Field of Search: 381113, 381120, 330174
• CPC Class Codes: B81B 7/008 MEMS characterised by an electronic circuit specially adapted for controlling or driving the same B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00
• CPC Class Codes: H04R 19/005 using semiconductor materials
• CPC Class Codes: H04R 19/04 Microphones H04R19/01 takes precedence
• CPC Class Codes: H04R 2201/003 Mems transducers or their use of the electrostatic type H04R19/005
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones

Abstract

A circuit for biasing a MEMS microphone includes a first group of serially-coupled transistors coupled between a first node and a second node, a second group of serially-coupled transistors coupled between the first node and the second node, and a voltage divider circuit coupled to the second node having a number of outputs, a first group of outputs being coupled to corresponding control nodes associated with the first group of serially-coupled transistors, and a second group of outputs different from the first group of outputs coupled to corresponding control nodes associated with the second group of serially-coupled transistors, the control nodes being either bulk nodes or gate nodes.

Claims

1. A circuit comprising:

a first plurality of serially-coupled transistors coupled between a first node and a second node;

a second plurality of serially-coupled transistors coupled between the first node and the second node; and

a voltage divider circuit in communication with the second node, the voltage divider circuit comprising a plurality of outputs, a first group of outputs of the plurality of outputs coupled to corresponding control nodes associated with the first plurality of serially-coupled transistors, and a second group of outputs of the plurality of outputs different from the first group of outputs coupled to corresponding control nodes associated with the second plurality of serially-coupled transistors, the control nodes comprising at least one of bulk nodes or gate nodes.

2. The circuit of claim 1, further comprising:

a third plurality of serially-coupled transistors coupled between the first node and a third node;

a fourth plurality of serially-coupled transistors coupled between the first node and the third node; and

an additional voltage divider circuit in communication with the third node, the additional voltage divider circuit comprising a plurality of outputs, a first group of outputs of the plurality of outputs coupled to corresponding control nodes associated with the third plurality of serially-coupled transistors, and a second group of outputs of the plurality of outputs different from the first group of outputs coupled to corresponding control nodes associated with the fourth plurality of serially-coupled transistors, the control nodes comprising at least one of bulk nodes or gate nodes.

3. The circuit of claim 1, comprising an associated impedance between the first and second nodes having a value in excess of one GOhm.

4. The circuit of claim 1, further comprising a MEMS microphone coupled to and biased by the second node.

5. The circuit of claim 1, further comprising a buffer amplifier interposed between the second node and the voltage divider circuit.

6. The circuit of claim 1, wherein the voltage divider circuit comprises a plurality of resistors having substantially the same resistance value.

7. The circuit of claim 1, wherein each output of the first group of outputs is voltage-shifted with respect to the second group of outputs.

8. A circuit comprising:

a first plurality of serially-coupled transistors coupled between a first node and a second node;

a second plurality of serially-coupled transistors coupled between the first node and the second node;

a first voltage divider circuit in communication with the second node, the first voltage divider circuit comprising a plurality of outputs, a first group of outputs of the plurality of outputs coupled to corresponding bulk nodes associated with the first plurality of serially-coupled transistors, and a second group of outputs of the plurality of outputs different from the first group of outputs coupled to corresponding bulk nodes associated with the second plurality of serially-coupled transistors; and

a second voltage divider circuit in communication with the second node, the second voltage divider circuit comprising a plurality of outputs, a first group of outputs of the plurality of outputs coupled to corresponding gate nodes associated with the first plurality of serially-coupled transistors, and a second group of outputs of the plurality of outputs different from the first group of outputs coupled to corresponding gate nodes associated with the second plurality of serially-coupled transistors.

9. The circuit of claim 8, further comprising:

a third plurality of serially-coupled transistors coupled between the first node and a third node;

a fourth plurality of serially-coupled transistors coupled between the first node and the third node;

a third voltage divider circuit in communication with the third node, the third voltage divider circuit comprising a first plurality of outputs coupled to corresponding bulk nodes associated with the third plurality of serially-coupled transistors, and a second plurality of outputs coupled to corresponding bulk nodes associated with the fourth plurality of serially-coupled transistors; and

a fourth voltage divider circuit in communication with the third node, the fourth voltage divider circuit comprising a first plurality of outputs coupled to corresponding gate nodes associated with the third plurality of serially-coupled transistors, and a second plurality of outputs coupled to corresponding gate nodes associated with the fourth plurality of serially-coupled transistors.

10. The circuit of claim 8, comprising an associated impedance between the first and second nodes having a value in excess of one GOhms.

11. The circuit of claim 8, further comprising a MEMS microphone coupled to and biased by the second node.

12. The circuit of claim 8, further comprising a buffer amplifier interposed between the second node and one of the first and second voltage divider circuits.

13. The circuit of claim 8, wherein one of the first and second voltage divider circuits comprises a plurality of resistors having substantially the same resistance value.

14. The circuit of claim 8, further comprising a temperature compensation circuit in communication with the second voltage divider circuit.

15. A method of operating a device comprising a first plurality of serially-coupled transistors between a first node and a second node, a second plurality of serially-coupled transistors between the first node and the second node, a third plurality of serially-coupled transistors coupled between the first node and a third node, and a fourth plurality of serially-coupled transistors coupled between the first node and the third node, the method comprising:

driving control nodes associated with the first plurality of serially-coupled transistors with a first set of voltages associated with the first and second nodes;

driving control nodes associated with the second plurality of serially-coupled transistors with a second set of voltages associated with the first and second nodes,

driving control nodes associated with the third plurality of serially-coupled transistors with a third set of voltages associated with the first and third nodes; and

driving control nodes associated with the fourth plurality of serially-coupled transistors with a fourth set of voltages associated with the first and third nodes,

wherein the control nodes comprise at least one of bulk nodes or gate nodes.

16. The method of claim 15, comprising setting an impedance between the first and second nodes to a value in excess of one GOhms.

17. The method of claim 15 further comprising biasing a MEMS microphone via the second node.

18. The method of claim 15, wherein the first and second sets of voltages each comprise a set of distinct voltage values.

19. The method of claim 15, further comprising generating at least one of the first or second sets of voltages from a low impedance source during a startup mode of operation.

20. A method of operating a device comprising a first plurality of serially-coupled transistors between a first node and a second node, and a second plurality of serially-coupled transistors between the first node and the second node, the method comprising:

driving control nodes associated with the first plurality of serially-coupled transistors with a first set of voltages associated with the first and second nodes;

driving control nodes associated with the second plurality of serially-coupled transistors with a second set of voltages associated with the first and second nodes,

wherein the control nodes comprise at least one of bulk nodes or gate nodes; and

biasing a MEMS microphone via the second node.

21. The method of claim 20, wherein the device further comprises a third plurality of serially-coupled transistors coupled between the first node and a third node, and a fourth plurality of serially-coupled transistors coupled between the first node and the third node, the method further comprising:

driving control nodes associated with the third plurality of serially-coupled transistors with a third set of voltages associated with the first and third nodes; and

driving control nodes associated with the fourth plurality of serially-coupled transistors with a fourth set of voltages associated with the first and third nodes,

wherein the control nodes comprise at least one of bulk nodes or gate nodes.

22. The method of claim 20, comprising setting an impedance between the first and second nodes to a value in excess of one GOhms.

23. The method of claim 20, wherein the first and second sets of voltages each comprise a set of distinct voltage values.

24. The method of claim 20, further comprising generating at least one of the first or second sets of voltages from a low impedance source during a startup mode of operation.