Electronic circuit for compensating a sensitivity drift of a hall effect element due to stress

• US 10,254,354 B2
• Filed: 09/17/2018
• Issued: 04/09/2019
• Est. Priority Date: 03/10/2016
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Inventors: Cesaretti, Juan Manuel
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US16/132,653
• Publication Number:
  US 20190018074A1
• Time in Patent Office: 204 Days
• Field of Search: 257427
• CPC Class Codes: G01L 1/2262 involving simple electrical bridges
• CPC Class Codes: G01R 27/08 Measuring resistance by measuring both voltage and current
• CPC Class Codes: G01R 33/0082 Compensation, e.g. compensating for temperature changes
• CPC Class Codes: G01R 33/07 Hall effect devices
• CPC Class Codes: G01R 33/093 using multilayer structures, e.g. giant magnetoresistance sensors thin magnetic films H01F10/00
• CPC Class Codes: H01L 21/02697 Forming conducting materials on a substrate
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10N 52/101 Semiconductor Hall-effect devices
• CPC Class Codes: H10N 52/80 Constructional details
• CPC Class Codes: H10N 59/00 Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00 MRAM devices H10B61/00

Abstract

The present disclosure is directed to an electronic circuit having a Hall effect element and a resistor bridge, all disposed over a common semiconductor substrate. The resistor bridge includes a first set of resistive elements having a first vertical epitaxial resistor and a first lateral epitaxial resistor coupled in series, and a second set of resistive elements having a second vertical epitaxial resistor and a second lateral epitaxial resistor coupled in series. The first set of resistive elements and the second set of resistive elements can be coupled in parallel. The resistor bridge can be configured to sense a stress value of the Hall effect element.

Claims

1. An electronic circuit comprising:

a semiconductor substrate;

an epitaxial layer disposed over a surface of the semiconductor substrate, the epitaxial layer having a first surface distal from the semiconductor substrate and a second surface proximate to the semiconductor substrate; and

,

a resistor bridge disposed upon the semiconductor substrate, the resistor bridge comprising;

a first set of resistive elements having a first vertical epitaxial resistor and a first lateral epitaxial resistor coupled in series, wherein the first vertical epitaxial resistor and the first lateral epitaxial resistor are disposed within the epitaxial layer; and

a second set of resistive elements having a second vertical epitaxial resistor and a second lateral epitaxial resistor coupled in series, wherein the second vertical epitaxial resistor and the second lateral epitaxial resistor are disposed within the epitaxial layer,

wherein the first set of resistive elements and the second set of resistive elements are coupled in parallel, and wherein the resistor bridge is operable to generate a differential signal responsive to a stress of the semiconductor substrate,

wherein the first and second vertical epitaxial resistors each comprise;

respective first and second pickups implanted upon and diffused into the first surface of the epitaxial layer; and

a respective buried structure disposed under the first surface of the epitaxial layer,

wherein a respective current passes from the respective first pickup, through a respective first region of the epitaxial layer, through the respective buried structure, and through a respective second region of the epitaxial layer to the respective second pickup.

2. The electronic circuit of claim 1, wherein each resistive element of the first and second sets of resistive elements have the same temperature coefficient.

3. The electronic circuit of claim 2, wherein a stress coefficient of the first vertical epitaxial resistor is equal to a stress coefficient of the second vertical epitaxial resistor.

4. The electronic circuit of claim 3, wherein a stress coefficient of the first lateral epitaxial resistors is equal to a stress coefficient of the second lateral epitaxial resistor.

5. The electronic circuit of claim 4, wherein stress coefficients of the first and second vertical epitaxial resistors are different from stress coefficients of the first and second lateral epitaxial resistors.

6. The electronic circuit of claim 5,

wherein each respective buried structure has a density of atoms that results in a respective first low resistance path with a respective first resistance lower than a resistance of the epitaxial layer, wherein the respective current passes through the respective first and second regions of the epitaxial layer in a direction substantially perpendicular to the first surface of the epitaxial layer, and wherein the respective buried structure has a respective first length dimension and a respective first width dimension, the respective first length dimension parallel to the respective first surface of the epitaxial layer.

7. The electronic circuit of claim 6, wherein the first and second lateral epitaxial resistors each comprise:

respective first and second pickups implanted upon and diffused into the first surface of the epitaxial layer, wherein a respective current passes from the first pickup, through a respective third region of the epitaxial layer, through a respective fourth region of the epitaxial layer, and through a respective fifth region of the epitaxial layer to the second pickup, wherein the respective current passes through the respective fourth region in a direction substantially parallel to the first surface of the epitaxial layer.

8. The electronic circuit of claim 7, further comprising a Hall effect element disposed upon the semiconductor substrate and proximate to the resistor bridge, wherein the resistor bridge is configured to sense a stress value of Hall effect element.

9. The electronic circuit of claim 8, further comprising a compensation circuit disposed upon the semiconductor substrate and coupled to the resistor bridge and operable to generate a compensation signal, wherein the compensation circuit is configured to receive the differential signal from the resistor bridge.

10. The electronic circuit of claim 9, further comprising an amplifier disposed upon the semiconductor substrate and coupled to the Hall effect element and the compensation circuit and operable to generate an amplified signal, wherein the amplifier is operable to change gain of the amplified signal depending upon a value of the compensation signal.

11. The electronic circuit of claim 8, further comprising:

an amplifier disposed upon the semiconductor substrate and coupled to the Hall effect element and operable to generate an amplified signal;

a first analog-to-digital converter disposed upon the semiconductor substrate and coupled to receive the amplified signal from the amplifier and operable to generate a first digital signal;

a processor disposed upon the semiconductor substrate and coupled to receive the first digital signal and operable to generate a processed signal wherein the processed single has a gain with respect to the first digital signal; and

a second analog-to-digital converter disposed upon the semiconductor substrate, coupled to the resistor bridge and operable to generate a second digital signal responsive to the differential signal, wherein the processor is further coupled to receive the second digital signal and operable to change the gain with respect to the first digital signal to generate the processed signal.

12. The electronic circuit of claim 9, further comprising:

a current generator operable to generate a drive current that passes through the Hall effect element, wherein the compensation circuit is coupled to the current generator and operable to provide the compensation signal to the current generator.

13. An electronic circuit comprising:

a semiconductor substrate;

an epitaxial layer disposed over a surface of the semiconductor substrate, the epitaxial layer having a first surface distal from the semiconductor substrate and a second surface proximate to the semiconductor substrate;

a Hall effect element comprising a bounded portion of the epitaxial layer; and

a resistor bridge disposed upon the semiconductor substrate and proximate to the Hall effect element, the resistor bridge comprising;

a first set of resistive elements having a first vertical epitaxial resistor and a first lateral epitaxial resistor coupled in series, wherein the first vertical epitaxial resistor and the first lateral epitaxial resistor are disposed within the epitaxial layer; and

a second set of resistive elements having a second vertical epitaxial resistor and a second lateral epitaxial resistor coupled in series, wherein the second vertical epitaxial resistor and the second lateral epitaxial resistor are disposed within the epitaxial layer,

wherein the first set of resistive elements and the second set of resistive elements are coupled in parallel, and wherein the resistor bridge is operable to sense a stress value of the semiconductor substrate and the Hall effect element, and wherein the resistor bridge is operable to generate a differential signal responsive to the stress value of the semiconductor substrate and the Hall effect element,

wherein the first and second vertical epitaxial resistors each comprise;

respective first and second pickups implanted upon and diffused into the first surface of the epitaxial layer; and

a respective buried structure disposed under the first surface of the epitaxial layer,

wherein a respective current passes from the respective first pickup, through a respective first region of the epitaxial layer, through the respective buried structure, and through a respective second region of the epitaxial layer to the respective second pickup.

14. The electronic circuit of claim 13, wherein each resistive element of the first and second sets of resistive elements have the same temperature coefficient.

15. The electronic circuit of claim 14, wherein a stress coefficient of the first vertical epitaxial resistor is equal to a stress coefficient of the second vertical epitaxial resistor.

16. The electronic circuit of claim 15, wherein a stress coefficient of the first lateral epitaxial resistors is equal to a stress coefficient of the second lateral epitaxial resistor.

17. The electronic circuit of claim 16, wherein stress coefficients of the first and second vertical epitaxial resistors are different from stress coefficients of the first and second lateral epitaxial resistors.

18. The electronic circuit of claim 13,

wherein each respective buried structure has a density of atoms that results in a respective first low resistance path with a respective first resistance lower than a resistance of the epitaxial layer, wherein the respective current passes through the respective first and second regions of the epitaxial layer in a direction substantially perpendicular to the first surface of the epitaxial layer, and wherein the respective buried structure has a respective first length dimension and a respective first width dimension, the respective first length dimension parallel to the respective first surface of the epitaxial layer.

19. The electronic circuit of claim 18, wherein the first and second lateral epitaxial resistors each comprise:

respective first and second pickups implanted upon and diffused into the first surface of the epitaxial layer, wherein a respective current passes from the first pickup, through a respective third region of the epitaxial layer, through a respective fourth region of the epitaxial layer, and through a respective fifth region of the epitaxial layer to the second pickup, wherein the respective current passes through the respective fourth region in a direction substantially parallel to the first surface of the epitaxial layer.

20. The electronic circuit of claim 19, further comprising a compensation circuit disposed upon the semiconductor substrate and coupled to the resistor bridge and operable to generate a compensation signal, wherein the compensation circuit is configured to receive the differential signal from the resistor bridge.

21. The electronic circuit of claim 20, further comprising an amplifier disposed upon the semiconductor substrate and coupled to the Hall effect element and the compensation circuit and operable to generate an amplified signal, wherein the amplifier is operable to change gain of the amplified signal depending upon a value of the compensation signal.

22. The electronic circuit of claim 19, further comprising:

an amplifier disposed upon the semiconductor substrate and coupled to the Hall effect element and the compensation circuit and operable to generate an amplified signal;

a first analog-to-digital converter disposed upon the semiconductor substrate and coupled to receive the amplified signal from the amplifier and operable to generate a first digital signal;

a processor disposed upon the semiconductor substrate and coupled to receive the first digital signal and operable to generate a processed signal wherein the processed single has a gain with respect to the first digital signal; and

a second analog-to-digital converter disposed upon the semiconductor substrate, coupled to the resistor bridge and operable to generate a second digital signal responsive to the differential signal, wherein the processor is further coupled to receive the second digital signal and operable to change the gain with respect to the first digital signal to generate the processed signal.

23. The electronic circuit of claim 20, further comprising:

a current generator operable to generate a drive current that passes through the Hall effect element, wherein the compensation circuit is coupled to the current generator and operable to provide the compensation signal to the current generator.