Display device

• US 10,254,607 B2
• Filed: 03/08/2018
• Issued: 04/09/2019
• Est. Priority Date: 10/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Akimoto, Kengo, Komori, Shigeki, Uochi, Hideki, Futamura, Tomoya, Kasahara, Takahiro
• Primary Examiner(s): Dulka, John P.
• Application Number:
  US15/915,663
• Publication Number:
  US 20180203312A1
• Time in Patent Office: 397 Days
• CPC Class Codes: G02F 1/136204 Arrangements to prevent high voltage or static electricity failures
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/0041 characterised by field-effect operation

Abstract

In order to take advantage of the properties of a display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area are necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer over the gate insulating film; a channel protective layer covering a region which overlaps with a channel formation region of the first oxide semiconductor layer; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and over the first oxide semiconductor layer. The gate electrode is connected to a scan line or a signal line, the first wiring layer or the second wiring layer is directly connected to the gate electrode.

Claims

1. A semiconductor device comprising:

a pixel portion comprising;

a pixel transistor; and

a capacitor comprising a first electrode and a second electrode;

a first protective circuit comprising;

a first non-linear element comprising a first oxide semiconductor layer;

a second non-linear element comprising a second oxide semiconductor layer; and

a third non-linear element comprising a third oxide semiconductor layer; and

a second protective circuit comprising;

a fourth non-linear element comprising a fourth oxide semiconductor layer;

a fifth non-linear element comprising a fifth oxide semiconductor layer; and

a sixth non-linear element comprising a sixth oxide semiconductor layer,

wherein the first protective circuit is electrically connected to the second protective circuit,

wherein a first conductive layer comprises;

a gate electrode of the first non-linear element; and

a first wiring,

wherein a second conductive layer comprises a gate electrode of the second non-linear element,

wherein a third conductive layer comprises a gate electrode of the third non-linear element,

wherein a fourth conductive layer comprises one of a source electrode and a drain electrode of the first non-linear element, and comprises one of a source electrode and a drain electrode of the third non-linear element,

wherein a fifth conductive layer comprises;

one of a source electrode and a drain electrode of the second non-linear element;

the other of the source electrode and the drain electrode of the third non-linear element; and

a second wiring,

wherein a sixth conductive layer comprises the other of the source electrode and the drain electrode of the first non-linear element, and comprises the other of the source electrode and the drain electrode of the second non-linear element,

wherein a seventh conductive layer comprises;

a gate electrode of the fourth non-linear element; and

a third wiring electrically connected to the second electrode of the capacitor,

wherein an eighth conductive layer comprises a gate electrode of the fifth non-linear element,

wherein a ninth conductive layer comprises a gate electrode of the sixth non-linear element,

wherein a tenth conductive layer comprises one of a source electrode and a drain electrode of the fourth non-linear element, and comprises one of a source electrode and a drain electrode of the sixth non-linear element,

wherein an eleventh conductive layer comprises;

one of a source electrode and a drain electrode of the fifth non-linear element; and

the other of the source electrode and the drain electrode of the sixth non-linear element,

wherein a twelfth conductive layer comprises the other of the source electrode and the drain electrode of the fourth non-linear element, and comprises the other of the source electrode and the drain electrode of the fifth non-linear element,

wherein the fourth conductive layer is in direct contact with the first conductive layer,

wherein the fifth conductive layer is in direct contact with the second conductive layer,

wherein the sixth conductive layer is in direct contact with the third conductive layer,

wherein the tenth conductive layer is in direct contact with the seventh conductive layer,

wherein the eleventh conductive layer is in direct contact with the eighth conductive layer,

wherein the twelfth conductive layer is in direct contact with the ninth conductive layer,

wherein one of a source electrode and a drain electrode of the pixel transistor is electrically connected to the first electrode of the capacitor, and

wherein one of the first wiring and the second wiring is electrically connected to the other of a source electrode and the drain electrode of the pixel transistor.

2. The semiconductor device according to claim 1,

wherein the fourth conductive layer is positioned over the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein the fifth conductive layer is positioned over the second oxide semiconductor layer and the third oxide semiconductor layer,

wherein the sixth conductive layer is positioned over the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein the tenth conductive layer is positioned over the fourth oxide semiconductor layer and the sixth oxide semiconductor layer,

wherein the eleventh conductive layer is positioned over the fifth oxide semiconductor layer and the sixth oxide semiconductor layer, and

wherein the twelfth conductive layer is positioned over the fourth oxide semiconductor layer and the fifth oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein the pixel portion further comprises a liquid crystal layer over the first non-linear element, the second non-linear element and the third non-linear element.

4. The semiconductor device according to claim 1, wherein the pixel portion further comprises an organic electroluminescent element.

5. The semiconductor device according to claim 1, wherein the pixel portion further comprises a contrast medium.

6. The semiconductor device according to claim 1, wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, the third oxide semiconductor layer, the fourth oxide semiconductor layer, the fifth oxide semiconductor layer and the sixth oxide semiconductor layer comprises In and Zn.

7. The semiconductor device according to claim 1, further comprising:

a first insulating layer between the first oxide semiconductor layer and the fourth conductive layer; and

a second insulating layer between the first oxide semiconductor layer and the sixth conductive layer.

8. The semiconductor device according to claim 1, further comprising:

a first insulating layer between the first conductive layer and the fourth conductive layer, between the second conductive layer and the fifth conductive layer, and between the third conductive layer and the sixth conductive layer; and

a second insulating layer between the seventh conductive layer and the tenth conductive layer, between the eighth conductive layer and the eleventh conductive layer, and between the ninth conductive layer and the twelfth conductive layer.

9. The semiconductor device according to claim 1, wherein the second wiring intersects the first wiring.

10. A semiconductor device comprising:

a pixel portion comprising;

a pixel transistor; and

a capacitor comprising a first electrode and a second electrode;

a first protective circuit comprising;

a first non-linear element comprising a first oxide semiconductor layer;

a second non-linear element comprising a second oxide semiconductor layer; and

a third non-linear element comprising a third oxide semiconductor layer; and

a second protective circuit comprising;

a fourth non-linear element comprising a fourth oxide semiconductor layer;

a fifth non-linear element comprising a fifth oxide semiconductor layer; and

a sixth non-linear element comprising a sixth oxide semiconductor layer,

wherein the first protective circuit is electrically connected to the second protective circuit,

wherein a first conductive layer comprises;

a gate electrode of the first non-linear element; and

a first wiring,

wherein a second conductive layer comprises a gate electrode of the second non-linear element,

wherein a third conductive layer comprises a gate electrode of the third non-linear element,

wherein a fourth conductive layer comprises one of a source electrode and a drain electrode of the first non-linear element, and comprises one of a source electrode and a drain electrode of the third non-linear element,

wherein a fifth conductive layer comprises;

one of a source electrode and a drain electrode of the second non-linear element;

the other of the source electrode and the drain electrode of the third non-linear element; and

a second wiring,

wherein a sixth conductive layer comprises the other of the source electrode and the drain electrode of the first non-linear element, and comprises the other of the source electrode and the drain electrode of the second non-linear element,

wherein a seventh conductive layer comprises;

a gate electrode of the fourth non-linear element; and

a third wiring electrically connected to the second electrode of the capacitor,

wherein an eighth conductive layer comprises a gate electrode of the fifth non-linear element,

wherein a ninth conductive layer comprises a gate electrode of the sixth non-linear element,

wherein a tenth conductive layer comprises one of a source electrode and a drain electrode of the fourth non-linear element, and comprises one of a source electrode and a drain electrode of the sixth non-linear element,

wherein an eleventh conductive layer comprises;

one of a source electrode and a drain electrode of the fifth non-linear element; and

the other of the source electrode and the drain electrode of the sixth non-linear element,

wherein a twelfth conductive layer comprises the other of the source electrode and the drain electrode of the fourth non-linear element, and comprises the other of the source electrode and the drain electrode of the fifth non-linear element,

wherein the fourth conductive layer is in direct contact with the first conductive layer,

wherein the fifth conductive layer is in direct contact with the second conductive layer,

wherein the sixth conductive layer is in direct contact with the third conductive layer,

wherein the tenth conductive layer is in direct contact with the seventh conductive layer,

wherein the eleventh conductive layer is in direct contact with the eighth conductive layer,

wherein the twelfth conductive layer is in direct contact with the ninth conductive layer,

wherein the first conductive layer is electrically connected to each of the first oxide semiconductor layer and the third oxide semiconductor layer, via the fourth conductive layer,

wherein the second conductive layer is electrically connected to each of the second oxide semiconductor layer and the third oxide semiconductor layer, via the fifth conductive layer,

wherein the third conductive layer is electrically connected to each of the first oxide semiconductor layer and the second oxide semiconductor layer, via the sixth conductive layer,

wherein the seventh conductive layer is electrically connected to each of the fourth oxide semiconductor layer and the sixth oxide semiconductor layer, via the tenth conductive layer,

wherein the eighth conductive layer is electrically connected to each of the fifth oxide semiconductor layer and the sixth oxide semiconductor layer, via the eleventh conductive layer,

wherein the ninth conductive layer is electrically connected to each of the fourth oxide semiconductor layer and the fifth oxide semiconductor layer, via the twelfth conductive layer,

wherein one of a source electrode and a drain electrode of the pixel transistor is electrically connected to the first electrode of the capacitor,

wherein third wiring is electrically connected to the second electrode of the capacitor,

wherein one of a source electrode and a drain electrode of the pixel transistor is electrically connected to the first electrode of the capacitor, and

wherein one of the first wiring and the second wiring is electrically connected to the other of a source electrode and the drain electrode of the pixel transistor.

11. The semiconductor device according to claim 10,

wherein the fourth conductive layer is positioned over the first oxide semiconductor layer and the third oxide semiconductor layer,

wherein the fifth conductive layer is positioned over the second oxide semiconductor layer and the third oxide semiconductor layer,

wherein the sixth conductive layer is positioned over the first oxide semiconductor layer and the second oxide semiconductor layer,

wherein the tenth conductive layer is positioned over the fourth oxide semiconductor layer and the sixth oxide semiconductor layer,

wherein the eleventh conductive layer is positioned over the fifth oxide semiconductor layer and the sixth oxide semiconductor layer, and

wherein the twelfth conductive layer is positioned over the fourth oxide semiconductor layer and the fifth oxide semiconductor layer.

12. The semiconductor device according to claim 10, wherein the pixel portion further comprises a liquid crystal layer over the first non-linear element, the second non-linear element and the third non-linear element.

13. The semiconductor device according to claim 10, wherein the pixel portion further comprises an organic electroluminescent element.

14. The semiconductor device according to claim 10, wherein the pixel portion further comprises a contrast medium.

15. The semiconductor device according to claim 10, wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, the third oxide semiconductor layer, the fourth oxide semiconductor layer, the fifth oxide semiconductor layer and the sixth oxide semiconductor layer comprises In and Zn.

16. The semiconductor device according to claim 10, further comprising:

a first insulating layer between the first oxide semiconductor layer and the fourth conductive layer; and

a second insulating layer between the first oxide semiconductor layer and the sixth conductive layer.

17. The semiconductor device according to claim 10, further comprising:

a first insulating layer between the first conductive layer and the fourth conductive layer, between the second conductive layer and the fifth conductive layer, and between the third conductive layer and the sixth conductive layer; and

a second insulating layer between the seventh conductive layer and the tenth conductive layer, between the eighth conductive layer and the eleventh conductive layer, and between the ninth conductive layer and the twelfth conductive layer.

18. The semiconductor device according to claim 10, wherein the second wiring intersects the first wiring.