Layout pattern proximity correction through fast edge placement error prediction

• US 10,254,641 B2
• Filed: 12/01/2016
• Issued: 04/09/2019
• Est. Priority Date: 12/01/2016
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Mailfert, Julien, Sriraman, Saravanapriyan, Tetiker, Mehmet Derya
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US15/367,060
• Publication Number:
  US 20180157161A1
• Time in Patent Office: 859 Days
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

Claims

1. A method of generating a look-up table (LUT) associating, for a plurality of features on a semiconductor substrate surface, values of one or more quantities characteristic of an edge placement error (EPE) with values of one or more quantities characteristic of an etch process, the features to be etched into a material stack on said substrate via a plasma-based etch process performed in a processing chamber under a set of process conditions, the method comprising:

(a) receiving the set of process conditions and the material stack composition;

(b) receiving a pattern of photoresist defining a set of features;

(c1) calculating, using a computer system, a first etch process characteristic value, the first etch process characteristic value corresponding to a first quantity characteristic of the etch process, under the set of process conditions, of a first selected feature from the set of features, wherein calculating the first etch process characteristic is performed using a computer model that relates an etched feature profile on a semiconductor device to one or more process conditions in an etcher;

(c2) calculating, using a computer system, a second etch process characteristic value, the second etch process characteristic value corresponding to the first characteristic of the etch process, under the set of process conditions, of a second selected feature from the set of features, wherein calculating the second etch process characteristic is performed using the computer model; and

(d1) including a first entry in the LUT associated with an edge of the first selected feature, the first entry comprising;

the first etch process characteristic value; and

a first EPE-characteristic (EPC) value corresponding to a quantity characteristic of an EPE of the edge of the first selected feature, said first EPC value generated by running a computerized etch profile model (EPM) to simulate etching under the set of process conditions of the material stack as overlaid with at least the portion of the pattern of photoresist corresponding to the first selected feature; and

(d2) determining to not include an entry in the LUT associated with an edge of the second selected feature and comprising the second etch process characteristic value, the determining based, at least in part, on the similarity of the second etch process characteristic value to the first etch process characteristic value,

wherein a LUT produced using (d1) and (d2) provides a computationally more efficient tool for determining values of the one or more quantities characteristic of edge placement error (EPE) in comparison to the computer model that relates an etched feature profile on a semiconductor device to one or more process conditions.

2. The method of claim 1, wherein it is determined in (d2) to not include the entry in the LUT for the second selected feature when the second etch process characteristic value is within 5% of the first etch process characteristic value.

3. The method of claim 1, wherein it is determined in (d2) to not include the entry in the LUT for the second selected feature when the second etch process characteristic value is within 2% of the first etch process characteristic value.

4. The method of claim 1, further comprising:

(c3) calculating a third etch process characteristic value, the third etch process characteristic value corresponding to the first quantity characteristic of the etch process during the etch, under the set of process conditions, of a third selected feature from the set of features; and

(d3) determining to not include an entry in the LUT associated with an edge of the third selected feature and comprising the third etch process characteristic value, the determining based, at least in part, on the similarity of the third etch process characteristic value to the first etch process characteristic value.

5. The method of claim 4, wherein:

in (d2) it is determined to not include the entry in the LUT for the second selected feature when the second etch process characteristic value is within 5% of the first etch process characteristic value; and

in (d3) it is determined to not include the entry in the LUT for the third selected feature when the third etch process characteristic value is within 5% of the first etch process characteristic value.

6. The method of claim 1, further comprising:

(c1′

) calculating a third etch process characteristic value, the third etch process characteristic value corresponding to a second quantity characteristic of the etch process, under the set of process conditions, of the first selected feature; and

(c2′

) calculating a fourth etch process characteristic value, the fourth etch process characteristic value corresponding to the second quantity characteristic of the etch process, under the set of process conditions, of the second selected feature;

 

wherein;

in (d1), the first entry in the LUT further comprises the third etch process characteristic value; and

in (d2), the determining is further based on the similarity of the fourth etch process characteristic value to the third etch process characteristic value.

7. The method of claim 6, wherein in (d2) it is determined to not include the entry in the LUT for the second selected feature when:

the second etch process characteristic value is within 5% of the first etch process characteristic value; and

the fourth etch process characteristic value is within 5% of the third etch process characteristic value.

8. The method of claim 6, wherein in (d2) the determining is based, at least in part, on a distance metric calculated between the first selected feature and the second selected feature, the distance metric calculated by a procedure comprising:

calculating a first difference indicator (DI) value indicative of the difference between the first etch process characteristic value and the second etch process characteristic value;

calculating a second DI value indicative of the difference between the third etch process characteristic value and the fourth etch process characteristic value; and

calculating a combined DI value indicative of the sum of the magnitudes of the first DI value and the second DI value.

9. The method of claim 8, wherein in (d2) the determining comprises comparing the distance metric to a reference value.

10. The method of claim 1, wherein in (d2) the determining is further based on the similarity of the first EPC value to a second EPC value, the second EPC value corresponding to a quantity characteristic of an EPE of the edge of the second selected feature, said second EPC value generated by running a computerized etch profile model (EPM) to simulate etching under the set of process conditions of the material stack as overlaid with at least the portion of the pattern of photoresist corresponding to the second selected feature.

11. The method of claim 1, wherein the first quantity characteristic of the etch process is a characteristic of in-feature plasma ion flux (IFPIF).

12. The method of claim 11, wherein the first etch process characteristic value is estimated based on a visibility kernel (VC) corresponding to the feature.

13. The method of claim 12, wherein the first etch process characteristic is calculated by a procedure comprising estimating the integral of the VC with the ion energy angular distribution function (IEADF) corresponding to one or more plasma ion fluxes (PIF) above the feature.

14. The method of claim 1, wherein the first quantity characteristic of the etch process is a characteristic of in-feature plasma neutral flux (IFPNF).

15. The method of claim 14, wherein the quantity characteristic of IFPNF is a loaded plasma flux above the feature which accounts for the presence of the substrate in the processing chamber.

16. The method of claim 1, wherein in (d2) the determining is further based on:

a sensitivity metric characteristic of the magnitude of variations in the first EPC value which result from changes in the first etch process characteristic value; and

/or

a sensitivity metric characteristic of the magnitude of variations in a second EPC value which result from changes in the second etch process characteristic value, the second EPC value corresponding to a quantity characteristic of an EPE of the edge of the second selected feature, said value generated by running a computerized etch profile model (EPM) to simulate etching under the set of process conditions of the material stack as overlaid with at least the portion of the pattern of photoresist corresponding to the second selected feature.

17. The method of claim 16, wherein the sensitivity metric characteristic of either or both of the first or second EPC values is calculated by estimating the partial derivative of the quantity characteristic of EPE with respect to the first quantity characteristic of the etch process (d[EPE]/d[etch process]) evaluated at either the first or second values of the EPC and the etch process characteristic.

18. The method of claim 17, wherein the sensitivity metric is calculated by a process comprising:

calculating a first difference indicator (DI) value indicative of the difference between the first and second EPC values;

calculating a second DI value indicative of the difference between the first and second etch process characteristic values; and

calculating a value indicative of d[EPE]/d[etch process] by calculating a value indicative of the ratio of the second to the first DI values.

19. The method of claim 18, wherein in (d2) the determining comprises comparing the sensitivity metric to a reference value.

20. The method of claim 19, wherein the first quantity characteristic of the etch process is a characteristic of in-feature plasma ion flux (IFPIF).

21. The method of claim 19, wherein the first quantity characteristic of the etch process is a characteristic of in-feature plasma neutral flux (IFPNF).

22. The method of claim 1, wherein the received set of process conditions include global processing chamber plasma fluxes of ion and/or neutral/radical plasma species.

23. The method of claim 1, further comprising:

(e) using a LUT produced using (d1) and (d2)

to enable development of a lithographic mask using values of EPC in the LUT, and/or

to enable etching a semiconductor substrate using a set of etch conditions identified using values of EPC in the LUT.

24. The method of claim 1, wherein operation (d)(2) limits the size of the LUT, thereby making the LUT more efficient to use.

25. A look-up table (LUT) comprising a plurality of entries corresponding to a plurality of edges of a plurality of features to be etched into a material stack on a semiconductor substrate surface via a plasma-based etch process performed in a processing chamber under a set of process conditions, the entries comprising a plurality of fields, the fields comprising:

an EPE field holding a value of a quantity characteristic of an edge placement error (EPE); and

one or more etch process fields holding values of one or more quantities characteristic of an etch process, the fields selected from;

an IFPIF field for holding a value of a quantity characteristic of in-feature plasma ion flux (IFPIF);

an IFPNF field for holding a value of a quantity characteristic of in-feature plasma neutral flux (IFPNF); and

an IFPDF field for holding a value of a quantity characteristic of in-feature passivant deposition flux (IFPDF);

wherein the average relative difference between pairs of nearest values held in fields of the table corresponding to each quantity characteristic of the etch process is greater than 5%,

wherein the LUT provides a computationally more efficient tool for determining values of the quantity characteristic of the EPE in comparison to a computer model that relates an etched feature profile on a semiconductor device to one or more process conditions, which computer model was used to calculate values of EPE used in the LUT.