Managing surprise hot plug in low power state

• US 10,254,821 B2
• Filed: 08/01/2017
• Issued: 04/09/2019
• Est. Priority Date: 08/01/2017
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gadey NV, K. L. Siva Prasad, Mehrotra, Samit, Wehage, Eric
• Primary Examiner(s): Zaman, Faisal M
• Application Number:
  US15/666,229
• Publication Number:
  US 20190041964A1
• Time in Patent Office: 616 Days
• Field of Search: 710304
• CPC Class Codes: G06F 1/1632 External expansion units, e.g. docking stations
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0026 PCI express
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus is provided which comprises: an input/output (I/O) port; a first circuitry to update an in-band presence detect field, based on communication via an in-band channel; a second circuitry to update an out-of-band presence detect field, based on communication via an out-of-band channel; and a third circuitry to update a presence detect state change field, wherein the third circuitry is to selectively ignore the out-of-band presence detect field and utilize the in-band presence detect field, while the third circuitry is to update the presence detect state change field.

Claims

1. An apparatus comprising:

an input/output (I/O) port;

a first circuitry to update an in-band presence detect field, based on communication via an in-band channel;

a second circuitry to update an out-of-band presence detect field, based on communication via an out-of-band channel; and

a third circuitry to update a presence detect state change field,

wherein the third circuitry is to selectively ignore the out-of-band presence detect field and utilize the in-band presence detect field, while the third circuitry is to update the presence detect state change field.

2. The apparatus of claim 1, further comprising:

a fourth circuitry to enable or disable surprise hot-plugging for the I/O port.

3. The apparatus of claim 1, wherein:

the third circuitry is to ignore the out-of-band presence detect field, based on the surprise hot-plugging being enabled for the I/O port.

4. The apparatus of claim 1, wherein:

the first circuitry is to update the in-band presence detect field, based on detecting, using communication via the in-band channel, of any device being added to or removed from the I/O port; and

the second circuitry is to update the out-of-band presence detect field, based on detecting, using communication via the out-of-band channel, of any device being added to or removed from the I/O port.

5. The apparatus of claim 1, further comprising:

a fourth circuitry to generate an interrupt, based on the presence detect state change field being asserted.

6. The apparatus of claim 5, further comprising:

a fifth circuitry to maintain a detect quiet state of the I/O port, until the interrupt is serviced and the presence detect state change field is cleared.

7. The apparatus of claim 6, wherein:

the fifth circuitry is to transition the I/O port to a detect active state, subsequent to the interrupt being serviced and the presence detect state change field being cleared.

8. The apparatus of claim 5, wherein:

the presence detect state change field is to be asserted, based on a surprise hot remove of a device from the I/O port.

9. The apparatus of claim 8, wherein the fifth circuitry is to maintain the detect quiet state of the I/O port, based on a surprise hot add followed by the surprise hot remove in the I/O port during a L1 state of the I/O port.

10. The apparatus of claim 1, wherein the I/O port is a Peripheral Component Interconnect Express (PCIe) port.

11. A system comprising:

a memory to store instructions;

a processor coupled to the memory;

an input/output (I/O) port, wherein the processor is to communicate with one or more devices via the I/O port;

a first circuitry to assert a first field, based on a surprise hot remove in the I/O port, the first field to indicate a presence detect state change of the I/O port; and

a second circuitry to maintain a detect quiet state of the I/O port, until the first field is de-asserted.

12. The system of claim 11, further comprising:

a third circuitry to generate an interrupt, based on the first field being asserted.

13. The system of claim 12, further comprising:

an interrupt handler to execute a hot remove routine, based on the interrupt,

wherein the first field is de-asserted subsequent to an execution of the hot remove routine.

14. The system of claim 11, wherein:

the second circuitry is to cause the I/O port to transition to a detect active state, subsequent to the first field being de-asserted.

15. The system of claim 14, further comprising:

a third circuitry to assert an in-band presence detect field, based on a surprise hot add in the I/O port and subsequent to the I/O port is to transition to the detect active state.

16. The system of claim 11, wherein the I/O port is a Peripheral Component Interconnect Express (PCIe) port.

17. An apparatus comprising:

an input/output (I/O) port;

a first circuitry to update a presence detect state change field (PRSDCH) associated with the I/O port; and

a second circuitry to delay transition from a detect quiet state of the I/O port to a detect active state of the I/O port, based on a state of the PRSDCH,

wherein the second circuitry is to delay transition from the detect quiet state to the detect active state, from a time the PRSDCH is updated until a time the PRSDCH is cleared.

18. The apparatus of claim 17, wherein the second circuitry is to delay transition from the detect quiet state to the detect active state, while the PRSDCH is being asserted.

19. The apparatus of claim 17, wherein the I/O port is a Peripheral Component Interconnect Express (PCIe) port.

20. The apparatus of claim 17, wherein:

the PRSDCH is to indicate a change of a state of the I/O port from occupied to unoccupied, or to indicate a change of the state of the I/O port from unoccupied to occupied;

the PRSDCH is different from a presence detect field; and

the presence detect field is to indicate whether the I/O port is occupied or unoccupied.