Delayed data release after programming to reduce read errors in memory

• US 10,255,000 B2
• Filed: 01/18/2017
• Issued: 04/09/2019
• Est. Priority Date: 01/18/2017
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Sharma, Sahil, Reusswig, Philip, Yang, Nian Niles, Sehgal, Rohit, Reddy, Gautham
• Primary Examiner(s): Dudek, Jr., Edward J
• Application Number:
  US15/408,943
• Publication Number:
  US 20180203642A1
• Time in Patent Office: 811 Days
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A memory device and associated techniques avoid reading memory cells immediately after programming when uncorrectable errors may be present. In one aspect, data is copied from one block to another block and a timer is started after the copying is completed. If a read command is received before the timer has expired, the read operation proceeds by reading the one block. If the read command is received after the timer has expired, the read operation proceeds by reading the another block. This approach is particular suitable when data is copied from single-level cell (SLC) blocks to multi-level cell (MLC) blocks in a folding operation. The duration of the timer can be increased at lower temperatures.

Claims

1. An apparatus, comprising:

a plurality of blocks of memory cells; and

a control circuit, the control circuit is configured to;

program a page of data received from a host in one block of the plurality of blocks;

in response to completion of the programming, start a first timer;

copying the page of data from the one block to another block of the plurality of blocks;

in response to completion of the copying, start a second timer;

when a request to read the page is received before expiration of the first timer, delay reading the page from the one block until the first timer has expired; and

when a request to read the page is received after expiration of the second timer, read the page from the another block.

2. The apparatus of claim 1, wherein:

the plurality of blocks comprise a virtual block; and

the virtual block comprise multiple physical blocks.

3. The apparatus of claim 1, wherein:

the one block comprises single-level memory cells;

the another block comprises multi-level memory cells; and

a control circuit is configured to start the copying in response to the one block being full.

4. The apparatus of claim 1, wherein:

the control circuit is configured to start the copying of the one block to the another block along with copying of an additional block of single-level memory cells to the another block in a folding operation.

5. The apparatus of claim 1, wherein:

the control circuit is configured to evaluate a portion of the page in the one block using an error correction code and confirm that no uncorrectable errors exist in the portion of the page in the one block before starting the copying.

6. The apparatus of claim 1, wherein:

the first timer indicates whether a short term data retention period has elapsed for the one block; and

the second timer indicates whether a short term data retention period has elapsed for the another block.

7. The apparatus of claim 1, wherein:

the control circuit is configured to modify a file system in response to expiration of the second timer to cause a logical block address to point to the another block instead of pointing to the one block.

8. The apparatus of claim 7, wherein:

the file system comprises a table;

the table comprises a bit, the bit having one value to indicate the logical block address points to the one block and another value to indicate the logical block address points to the another block; and

the control circuit is configured to change the bit from the one value to the another value in response to expiration of the second timer.

9. The apparatus of claim 1, wherein:

the first timer indicates whether a data retention period has elapsed for the one block; and

the second timer indicates whether a data retention period has elapsed for the another block.

10. The apparatus of claim 1, wherein:

a duration of the first timer increases when a temperature decreases.

11. A method, comprising:

programming a page of data to one block;

starting a first timer in response to completion of the programming;

copying the page of data from the one block to another block;

starting a second timer in response to completion of the copying;

receiving a request to read the page after the starting of the first timer and when the first timer has not yet expired; and

delaying reading of the page from the one block until the first timer has expired.

12. The method of claim 11, further comprising:

copying the page from the one block to the another block along with copying of an additional page of an additional block to the another block when the one block and the additional block become full.

13. The method of claim 11, wherein:

the page of data is copied from single-level memory cells in the one block to multi-level memory cells in the another block.

14. The method of claim 11, further comprising:

in response to expiration of the second timer, modifying a file system to cross reference a logical block address to the another block in place of the one block.

15. The method of claim 11, further comprising:

increasing a duration of the first timer when a temperature decreases.

16. The method of claim 11, wherein:

the reading the page from the another block uses a nominal read voltage.

17. An apparatus, comprising:

means for programming data in one block;

a first timer which indicates whether a short term data retention period has elapsed for the one block since completion of the programming;

means for copying the data from the one block to another block;

a second timer which indicates whether a short term data retention period has elapsed for the another block since completion of the copying; and

means for reading the data from the one block in response to a read command, wherein the reading of the data occurs from the one block when the first timer expires, when the read command is received before the first timer expires.

18. The apparatus of claim 17, wherein:

the reading of the data occurs from the one block when the read command is received after expiration of the first timer and before expiration of the second timer.

19. The apparatus of claim 17, wherein:

the reading of the data occurs from the another block when the read command is received after expiration of the first timer and the second timer.

20. The apparatus of claim 17, wherein:

the short term data retention period for the one block increases when a temperature decreases.